HD6432160 RENESAS [Renesas Technology Corp], HD6432160 Datasheet - Page 503

• Manufacturer Part Number: HD6432160
• Description: Hitachi 16-Bit Single-Chip Microcomputer
• Manufacturer: RENESAS [Renesas Technology Corp]

14. Note on ACKE and TRS bits in slave mode
16.6.1
The IIC operation can be enabled or disabled using the module stop control register. The initial
setting is for the IIC operation to be halted. Register access is enabled by canceling module stop
mode. For details, refer to section 26, Power-Down Modes.
In the I
mode (TRS = 1) and then the address is received in slave mode without performing appropriate
processing, interrupt handling may start at the rising edge of the 9th clock pulse even when the
address does not match. Similarly, if the start condition or address is transmitted from the
master device in slave transmit mode (TRS = 1), the IRIC flag may be set after the ICDRE flag
is set and 1 received as the acknowledge bit value (ACKB = 1), thus causing an interrupt
source even when the address does not match.
To use the I
A. When having received 1 as the acknowledge bit value for the last transmit data at the end
B. Set receive mode (TRS = 0) before the next start condition is input in slave mode.
of a series of transmit operation, clear the ACKE bit in ICCR once to initialize the ACKB
bit to 0.
Complete transmit operation by the procedure shown in figure 16.24, in order to switch
from slave transmit mode to slave receive mode.
Module Stop Mode Setting
2
C bus interface, if 1 is received as the acknowledge bit value (ACKB = 1) in transmit
2
C bus interface module in slave mode, be sure to follow the procedures below.
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