HD6432160 RENESAS [Renesas Technology Corp], HD6432160 Datasheet - Page 654

• Manufacturer Part Number: HD6432160
• Description: Hitachi 16-Bit Single-Chip Microcomputer
• Manufacturer: RENESAS [Renesas Technology Corp]

25.4
The bus master clock select circuit selects a clock to supply the bus master with either the system
clock (ø) or medium-speed clock (ø/2, ø/4, ø/8, ø/16, or ø/32) by the SCK2 to SCK0 bits in
SBYCR.
25.5
The subclock input circuit controls subclock input from the EXCL pin. To use the subclock, a
32.768-kHz external clock should be input from the EXCL pin. At this time, the P96DDR bit in
P9DDR should be cleared to 0, and the EXCLE bit in LPWRCR should be set to 1.
Subclock input conditions are shown in table 25.5. When the subclock is not used, subclock input
should not be enabled.
Table 25.5 Subclock Input Conditions
Item
Subclock input pulse width
low level
Subclock input pulse width
high level
Subclock input rising time
Subclock input falling time
25.6
To remove noise from the subclock input at the EXCL pin, the subclock is sampled by a divided ø
clock. The sampling frequency is set by the NESEL bit in LPWRCR.
The subclock is not sampled in subactive mode, subsleep mode, or watch mode.
Rev. 2.0, 08/02, page 614 of 788
Bus Master Clock Select Circuit
Subclock Input Circuit
Subclock Waveform Forming Circuit
EXCL
t
EXCLr
t
Symbol
t
t
t
EXCLL
EXCLH
EXCLr
EXCLf
Figure 25.7 Subclock Input Timing
t
EXCLH
Min
—
—
—
—
Vcc = 2.7 to 5.5 V
Typ
15.26
15.26
—
—
t
EXCLf
t
EXCLL
Max
—
—
10
10
Unit
ns
ns
V
s
s
CC
× 0.5
Measurement
Condition
Figure 25.7