HD6432160 RENESAS [Renesas Technology Corp], HD6432160 Datasheet - Page 489

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HD6432160

Manufacturer Part Number
HD6432160
Description
Hitachi 16-Bit Single-Chip Microcomputer
Manufacturer
RENESAS [Renesas Technology Corp]
Datasheet
16.4.8
Setting the SW bit to 1 in DDCSWR enables formatless mode to be selected as the IIC_0
operating mode. Switching from formatless mode to the I
automatically when a falling edge is detected on the SCL pin.
The following four preconditions are necessary for this operation:
A common data pin (SDA) for formatless and I
Separate clock pins for formatless operation (VSYNCI) and I
A fixed 1 level for the SCL pin during formatless operation (the SCL pin does not output a low
level)
Settings of bits other than TRS in ICCR that allow I
When FS = 1 and FSX = 1 (clocked synchronous serial format)
(a) Data transfer ends with ICDRE=0 at transmission, or ICDRF=0 at reception.
(b) Data transfer ends with ICDRE=1 at transmission, or ICDRF=1 at reception.
SCL
SDA
IRIC
User processing
SCL
SDA
IRIC
User processing
Automatic Switching from Formatless Mode to I
7
7
7
7
Figure 16.28 IRIC Setting Timing and SCL Control (3)
8
8
8
8
1
1
Clear IRIC
Clear IRIC
2
C bus format operation
2
2
2
C bus format operation
2
C bus format (slave mode) is performed
Write to ICDR (transmit)
or read from ICDR (receive)
2
C Bus Format
2
C bus format operation (SCL)
Rev. 2.0, 08/02, page 449 of 788
3
3
1
4
1
4
Clear IRIC

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