TMP91xy40FG Toshiba, TMP91xy40FG Datasheet - Page 94

• Manufacturer Part Number: TMP91xy40FG
• Manufacturer: Toshiba

Specifications of TMP91xy40FG

• Package: LQFP100
• Rom Types(m=mask,p=otp, F=flash,e=eeprom): M/F
• Rom Combinations: 128
• Ram Combinations: 4
• Architecture: 16-bit CISC
• Usb/spi Channels: -
• Uart/sio Channels: 4
• I2c/sio Bus Channels: -
• (s)dram Controller: -
• Adc 10-bit Channel: 4
• Da Converter: -
• Timer 8-bit Channel: 4
• Timer 16-bit Channel: 3
• Pwm 8-bit Channels: -
• Pwm 16-bit Channels: -
• Cs/wait Controller: -
• Dual Clock: Y
• Number Of I/o Ports: 61
• Power Supply Voltage(v): 2.2 to 3.6

TC5SEL = 0
fc/2
fc/2
fc/2
fc/2
fc/3
fc/2
fc
11
7
5
3
[Hz]
(2) 8-bit pulse width modulation (PWM) output mode (TC5 and TC6)
Source Clock
resolution of 8 bits. The counter counts up internal clock pulses. When a match
between the counter value and the PWREGi value is detected, the timer flip-flop (F/Fi)
is toggled. The counter then continues counting up. When an overflow occurs, the timer
F/Fi is toggled again and the counter is cleared. The output from the timer F/Fi is
output on the TCiOUT pin after being inverted. When an overflow occurs, an INTTMRi
interrupt is generated.
enabling the PWREGi value to be changed while the timer is running. While the timer
is running, the value written to the PWREGi is shifted into the shift register and
becomes valid by an INTTMRi interrupt. This feature makes it possible to change the
pulse width continuously. When the timer is not running, the value written to the
PWREGi is immediately shifted into the shift register.
register value is returned instead of the value set in the PWREGi. This means that the
new value written to the PWREGi cannot be read out until an INTTMRi interrupt
occurs; up to that point the previous PWREGi value is read out.
This mode is used to generate pulse width modulated (PWM) signals with a
In the PWM mode, the PWREGi register is serially connected to a shift register,
When a read instruction is executed on the PWREGi during PWM output, the shift
TC5SEL = 1
Note 1: In the PWM mode, the PWREGi register should be written to immediately after an INTTMRi
Note 2: When the timer is stopped during PWM output, the TCiOUT pin retains its current output state. After
Note 3: i = 5, 6
fs
fs/2
3
[Hz]
interrupt occurred (normally in the INTTMRi interrupt service routine). If a write to the PWREGi and
an INTTMRi interrupt occur simultaneously, an unstable value is shifted into the shift register,
causing unexpected pulses to be generated until the next INTTMRi interrupt occurs.
the timer stops, the TCiOUT pin state can be changed to a desired level by using TCiCR1<TFFi>.
Be careful not to set TCiCR1<TFFi> at the same time as stopping the timer.
296.3 ns
111.1 ns
fc = 27 MHz
Table 3.9.5 PWM Output Mode
75.9 μs
74.1 ns
37.0 ns
4.7 μs
1.2 μs
Resolution
91CW40-92
fs = 32.768 kHz
244.14 μs
30.5 μs
fc = 27 MHz
303.4 μs
75.9 μs
28.4 μs
19.0 μs
19.4 ms
9.5 μs
1.2 ms
Repeat Cycle
fs = 32.768 kHz
62.5 ms
7.81 ms
TMP91CW40
2008-09-19