TMP91xy40FG Toshiba, TMP91xy40FG Datasheet - Page 75

• Manufacturer Part Number: TMP91xy40FG
• Manufacturer: Toshiba

Specifications of TMP91xy40FG

• Package: LQFP100
• Rom Types(m=mask,p=otp, F=flash,e=eeprom): M/F
• Rom Combinations: 128
• Ram Combinations: 4
• Architecture: 16-bit CISC
• Usb/spi Channels: -
• Uart/sio Channels: 4
• I2c/sio Bus Channels: -
• (s)dram Controller: -
• Adc 10-bit Channel: 4
• Da Converter: -
• Timer 8-bit Channel: 4
• Timer 16-bit Channel: 3
• Pwm 8-bit Channels: -
• Pwm 16-bit Channels: -
• Cs/wait Controller: -
• Dual Clock: Y
• Number Of I/o Ports: 61
• Power Supply Voltage(v): 2.2 to 3.6

Timer Register
Internal Window Gate Pulse Setting Register
Timer/Counter 1 Control Register 1
(0941H, 0940H)
TREG1B
TC1CR1
(0943H)
(0944H)
3.8.2
TREG1A
Control
Note 1:
Note 2:
Note 3:
Note 4:
Note 5:
Note 6:
Note 7:
Note 8:
Note 9:
Note 10: In NORMAL mode, changing TC1CR1 and TREG1A while selecting fs (TC1CR2<TC1SEL>=”1”) is prohibited.
Note 11: In SLOW mode, do not set TC1CR2<TC1SEL>=0.
Note 12: “−“indicates a setting that must not be selected.
Note: WGPSCK = 01
TC1C
(TC1CR1/TC1CR2), timer register (TREG1A) and internal window gate pulse setting
register (TREG1B).
TC1CK
TC1M
TC1C
TC1S
7
7
The timer/counter 1 (TC1) is controlled by the timer/counter 1 control registers
Ta
Tb
15
fc: High-frequency clock [Hz], fs: Low-frequency clock [Hz], *: Don’t care
After the lower byte of the timer register (TREG1AL) is written, match detection is temporarily disabled until a write to
the upper byte (TREG1AH) is completed. (It is not possible to modify only the lower byte of the timer register.) Also
note that match detection is enabled again after one machine cycle has elapsed upon completion of a write to the
upper byte.
Before changing the operating mode, source clock and edge selection, be sure to stop the timer/counter
(<TC1S>=00). TC1CR1<TC1S> and TC1CR1<TC1C> must not be changed simultaneously.
The source clock can be set to fc, fc/2 and fs only in the pulse width measurement mode (in NORMAL or IDLE2
mode).
When a read instruction is executed on the timer register (TREG1A), the counter immediate value, not the value
written to the TREG1A is read out. Before reading the TREG1A, therefore, make sure that the timer/counter is
stopped; otherwise an undefined value may be read out.
The timer register value should be TREG1A ≥ 1.
In the timer or pulse width measurement mode, select an internal clock as the source clock (TC1CR1<TC1CK>).
In the event counter mode, select an external clock as the source clock (TC1CR1<TC1CK>).
Since the timer register (TREG1A) has different write and read values, read-modify-write instructions must not be
used on this register.
Window gate pulse “H” level period
TC1 start control
TC1 source clock select
TC1 operating mode select
6
6
Window gate pulse “L” level period
14
TC1S
Ta
Figure 3.8.2 TC1 Timer Register/Window Gate Pulse Setting Register/Control Register
13
5
5
TREG1AH (0941H)
12
4
4
11
TC1CK
10
3
3
91CW40-73
00: Stop and clear counter (and overflow flag)
10: Start TC1
00: Timer/event counter mode
01: Reserved
10: Pulse width measurement mode
11: Frequency measurement mode
*1: Reserved
000
001
010
011
100
101
110
111
0: Clear counter and overflow flag
9
(Automatically set to 1 after clearing)
(16− Ta) × 2
(16 − Tb) × 2
2
2
Tb
8
fc/2 (Note 4)
1
1
TC1SEL=0
fc (Note 4)
TC1M
13
7
13
fc/2
fc/2
fc/2
fc/2
fc/2
/fc or (16 − Ta) × 2
/fc or (16 − Tb) × 2
External clock (ECIN1 pin input)
7
11
13
23
3
Read/Write (Initial value: 0000 0000 0000 0000)
0
0
6
(Initial value: 0000 0000)
(Initial value: 1000 0000)
5
TREG1AL (0940H)
TC1SEL=1
fs (Note 4)
4
fs/2
5
fs/2
fs/2
/fs [s]
5
−
−
−
/fs [s]
15
3
5
3
2
TMP91CW40
[Hz]
2008-09-19
1
R/W
R/W
0