TMP91xy40FG Toshiba, TMP91xy40FG Datasheet - Page 34

• Manufacturer Part Number: TMP91xy40FG
• Manufacturer: Toshiba

Specifications of TMP91xy40FG

• Package: LQFP100
• Rom Types(m=mask,p=otp, F=flash,e=eeprom): M/F
• Rom Combinations: 128
• Ram Combinations: 4
• Architecture: 16-bit CISC
• Usb/spi Channels: -
• Uart/sio Channels: 4
• I2c/sio Bus Channels: -
• (s)dram Controller: -
• Adc 10-bit Channel: 4
• Da Converter: -
• Timer 8-bit Channel: 4
• Timer 16-bit Channel: 3
• Pwm 8-bit Channels: -
• Pwm 16-bit Channels: -
• Cs/wait Controller: -
• Dual Clock: Y
• Number Of I/o Ports: 61
• Power Supply Voltage(v): 2.2 to 3.6

X1
A0∼A23
D0∼D15
RD
WR / HWR
1st to 3rd states:
4th to 5th states:
6th state:
7th and 8th states: Micro DMA write cycle
Note 1: If the source address area uses an 8-bit bus, additional two states are needed.
Note 2: If the destinatin address area uses an 8-bit bus, additional two states are needed.
address increment mode (with all address areas accessed with a 16-bit data bus, no
wait cycles, and even-numbered source/destination addresses).
1 state
If the source address area uses a 16-bit bus but starts with an odd-numbered address, additional two states are
needed.
DM1
If the destination address area uses a 16-bit bus but starts with an odd-numbered address, additional two states
are needed.
the counter defaults to 0000H) can be performed for a single interrupt source.
soft start.
The transfer counter consists of 16 bits so that up to 65536 micro DMA transfers (if
The micro DMA supports 19 interrupt sources as shown in Table 3.4.1 as well as a
Figure 3.4.2 shows micro DMA cycles for 2-byte transfer in the transfer destination
each transfer mode, the transfer source and destination addresses can be
incremented, decremented or fixed after the transfer of a single unit of data. This
ability to select various modes facilitates data transfer from I/O to memory,
memory to I/O, and I/O to I/O. For details of transfer modes, see “(4) Transfer
mode registers”.
The micro DMA supports three transfer modes: 1 byte, 2 bytes or 4 bytes. For
Address
DM2
Instruction fetch cycles (prefetching next instruction code).
If three or more bytes of instruction code are stored in the instruction
queue buffer, these cycles become dummy cycles.
Micro DMA read cycles
Dummy cycle (address bus left in the 5th state).
DM3
Figure 3.4.2 Micro DMA Cycles
DM4
91CW40-32
Note 1
Source
Input
DM5
DM6
DM7
Destination
Note 2
Output
DM8
Address + 2
TMP91CW40
2008-09-19