TMP91xy40FG Toshiba, TMP91xy40FG Datasheet - Page 167

• Manufacturer Part Number: TMP91xy40FG
• Manufacturer: Toshiba

Specifications of TMP91xy40FG

• Package: LQFP100
• Rom Types(m=mask,p=otp, F=flash,e=eeprom): M/F
• Rom Combinations: 128
• Ram Combinations: 4
• Architecture: 16-bit CISC
• Usb/spi Channels: -
• Uart/sio Channels: 4
• I2c/sio Bus Channels: -
• (s)dram Controller: -
• Adc 10-bit Channel: 4
• Da Converter: -
• Timer 8-bit Channel: 4
• Timer 16-bit Channel: 3
• Pwm 8-bit Channels: -
• Pwm 16-bit Channels: -
• Cs/wait Controller: -
• Dual Clock: Y
• Number Of I/o Ports: 61
• Power Supply Voltage(v): 2.2 to 3.6

3.14 Program Patch Logic
3.14.1
Address compare registers (Bank2)
Address compare registers (Bank3)
Address compare registers (Bank4)
Address compare registers (Bank5)
Address compare registers (Bank0)
Address compare registers (Bank1)
(ROMCMP20 to ROMCMP22)
(ROMCMP30 to ROMCMP32)
(ROMCMP40 to ROMCMP42)
(ROMCMP50 to ROMCMP52)
(ROMCMP00 to ROMCMP02)
(ROMCMP10 to ROMCMP12)
code in the internal ROM. Patch program code must be read into the internal RAM from
external memory during the startup routine.
significant code correction can be performed by replacing program code with single-byte
instruction code which generates a software interrupt (SWI) to make a branch to a specified
location in the internal RAM area.
the program code in the internal I/O, internal RAM and external ROM areas.
following sections, any references to bank0 also apply to other banks.
The TMP91CW40 has a program patch logic, which enables the user to fix the program
Up to six 2-byte sequences (12 bytes in total) can be replaced with patch code. More
The program patch logic only compares addresses in the internal ROM area; it cannot fix
Each of six banks is independently programmable, and functionally equivalent. In the
Block Diagram
Address bus
CPU
Figure 3.14.1 Program Patch Logic Diagram
ROMRD
91CW40-165
Match signal
Output enable
ROMRD
Data substitution registers (Bank1)
Data substitution registers (Bank4)
Data substitution registers (Bank2)
Data substitution registers (Bank3)
Data substitution registers (Bank5)
Data substitution registers (Bank0)
(ROMSUB1L/H)
(ROMSUB4L/H)
(ROMSUB2L/H)
(ROMSUB3L/H)
(ROMSUB5L/H)
(ROMSUB0L/H)
ROM
Data bus
TMP91CW40
2008-09-19