TMP91xy40FG Toshiba, TMP91xy40FG Datasheet - Page 134

• Manufacturer Part Number: TMP91xy40FG
• Manufacturer: Toshiba

Specifications of TMP91xy40FG

• Package: LQFP100
• Rom Types(m=mask,p=otp, F=flash,e=eeprom): M/F
• Rom Combinations: 128
• Ram Combinations: 4
• Architecture: 16-bit CISC
• Usb/spi Channels: -
• Uart/sio Channels: 4
• I2c/sio Bus Channels: -
• (s)dram Controller: -
• Adc 10-bit Channel: 4
• Da Converter: -
• Timer 8-bit Channel: 4
• Timer 16-bit Channel: 3
• Pwm 8-bit Channels: -
• Pwm 16-bit Channels: -
• Cs/wait Controller: -
• Dual Clock: Y
• Number Of I/o Ports: 61
• Power Supply Voltage(v): 2.2 to 3.6

(03D0H)
LCDCR
3.11.2 Control
Note 1:
Note 2:
Note 3:
Note 4:
Note 5:
Note 6
EDSP
the LCDCR is used to enable LCD display.
VFSEL
DUTY
BRES
EDSP
SLF
7
The LCD driver is controlled by the LCD control register (LCDCR). The <EDSP> bit in
When <BRES>=0, V
satisfied. Ignoring these conditions may not only affect the quality of LCD display but also damage the device
due to overcurrent that flows through ports.
The <SLF1:0> and <DUTY1:0> fields should be set when <EDSP>=0. (Nor is it allowed to set these fields
with the same instruction that sets <EDSP> to 0. ) Otherwise, the expected duty cannot be obtained and the
LCD cannot be displayed properly.
The reference clock (LCDCLK) for the base frequency of the LCD driver is independent of the system clock
and can be switched between low-frequency (fs) and high-frequency (fc) by the programming of the SYSCR3
<LCDCKMOD> bit. For proper operation of the LCD, be careful about the following points:
When the low-frequency (fs) clock is used for the system clock, it is recommended to set LCDCLK to
low-frequency (fs) in the application’s startup routine and to always use the low-frequency (fs) clock for
LCDCLK.
When the device enters STOP mode, the <EDSP> bit is automatically cleared to 0. If HALT mode is activated
immediately after display data is written to the LCDREG, the LCD is not displayed correctly and the device
immediately enters HALT mode.
After exiting STOP mode, do not make any settings for the LCD driver until the warming up of fs has
completed. This can be checked by the SYSCR0 register.
When used as LCD pins, COM output pins output low level and SEG output pins are placed in a
high-impednce state when the <EDSP> bit is cleared to 0 (except when SEG output pins are used as ports).
When LCDCR2<MSEG07>=1, SEG0 to SEG7 pins output low level.
To change the SYSCR3<LCDCKMOD> bit, the <EDSP> bit must be 0.
BRES
• Before changing LCDCLK to low-frequency (fs), start up the low-frequency oscillator (fs) by
•
• Before changing the system clock from high-frequency (fc) to low-frequency (fs), make sure to set
Base frequency [Hz]
LCD drive method
Voltage reducer frequency
Voltage reducer
enable/disable
LCD display control
[Hz]
6
programming SYSCR0<XTEN> and make sure that the warming-up period has completed by checking
SYSCR0<WUEFL>.
LCDCLK to low-frequency (fs).
It is not allowed to set the system clock to low-frequency (fs) and LCDCLK to high-frequency (fc).
5
Figure 3.11.2 LCD Driver Control Register (1)
VFSEL
DD
4
≥ V
3
≥ V
3
91CW40-132
2
DUTY
00
01
10
11
00: 1/4 duty (1/3 bias)
01: 1/3 duty (1/3 bias)
10: 1/2 duty (1/2 bias)
11: Static
00
01
10
11
≥ V
0: Disable (Use external divider resistors)
1: Enable
0: Disable
1: Enable
1
<LCDCKMOD>=0
<LCDCKMOD>=0
≥ V
2
SS
SYSCR3
SYSCR3
fc/2
fc/2
fc/2
fc/2
fc/2
fc/2
fc/2
fc/2
must be satisfied. When <BRES>=1, V
SYSCR1<SYSCK>=0
SYSCR1<SYSCK>=0
19
18
17
16
11
10
9
8
1
SLF
<LCDCKMOD>=1
<LCDCKMOD>=1
0
SYSCR3
SYSCR3
fs/2
fs/2
fs/2
fs/2
fs/2
fs/2
fs/2
fs
(Initial value: 0000 0000)
10
9
8
7
3
2
<LCDCKMOD>=1
<LCDCKMOD>=1
<SYSCK>=1
<SYSCK>=1
SYSCR1
SYSCR3
SYSCR1
SYSCR3
DD
fs/2
fs/2
fs/2
fs/2
fs/2
fs/2
fs/2
fs
= V
10
9
8
7
3
2
TMP91CW40
3
2008-09-19
must be
R/W