TMP91xy40FG Toshiba, TMP91xy40FG Datasheet - Page 36

• Manufacturer Part Number: TMP91xy40FG
• Manufacturer: Toshiba

Specifications of TMP91xy40FG

• Package: LQFP100
• Rom Types(m=mask,p=otp, F=flash,e=eeprom): M/F
• Rom Combinations: 128
• Ram Combinations: 4
• Architecture: 16-bit CISC
• Usb/spi Channels: -
• Uart/sio Channels: 4
• I2c/sio Bus Channels: -
• (s)dram Controller: -
• Adc 10-bit Channel: 4
• Da Converter: -
• Timer 8-bit Channel: 4
• Timer 16-bit Channel: 3
• Pwm 8-bit Channels: -
• Pwm 16-bit Channels: -
• Cs/wait Controller: -
• Dual Clock: Y
• Number Of I/o Ports: 61
• Power Supply Voltage(v): 2.2 to 3.6

(DMAM0 to DMAM3)
Note 1: n: Corresponding micro DMA channel (0 to 3)
Note 2:
Note 3:
0
0
0
0
0
1
1
0
0
1
1
0
0
0
0
1
0
1
0
1
DMADn+/DMASn+: Post-increment (incrementing the register value after transfer)
DMADn−/DMASn−: Post-decrement (decrementing the register value after transfer)
In the table, “I/O” means a fixed address while “memory” means an address that can be incrementaed or decremented.
Execution time:
Any code other than those listed above must not be written to transfer mode registers.
0
Z
Z
Z
Z
Z
0
(4) Transfer mode registers: DMAM0 to DMAM3
Z
Z
Z
Z
Z
0
ZZ: 0 = Byte transfer, 1 = Word transfer, 2 = 4-byte transfer, 3 = Reserved
Destination address increment mode ....................... I/O to memory
(DMADn+) ← (DMASn)
DMACn ← DMACn − 1
if DMACn = 0 then INTTC occurs
Destination address decrement mode ...................... I/O to memory
(DMADn−) ← (DMASn)
DMACn ← DMACn − 1
if DMACn = 0 then INTTC occurs
(DMADn) ← (DMASn+)
DMACn ← DMACn − 1
if DMACn = 0 then INTTC occurs
Source address decrement mode ........................... Memory to I/O
(DMADn) ← (DMASn−)
DMACn ← DMACn−1
if DMACn = 0 then INTTC occurs
Fixed address mode ................................................. I/O to I/O
(DMADn) ← (DMASn)
DMACn ← DMACn − 1
if DMACn = 0 then INTTC occurs
Counter mode
DMASn ← DMASn + 1
DMACn ← DMACn − 1
if DMACn = 0 then INTTC occurs
Source address increment mode.............................. Memory to I/O
Mode
The time required to complete transferring a single unit of data when a 16-bit bus is used for the source
and destination address areas and no wait cycles are inserted.
Clock settings: fc = 27 MHz, cloock gear = x1 (fc)
Counting the number of interrupts that have occurred
Note: The upper three bits of data written to these
registers must always be “0”.
91CW40-34
Byte/word transfer
Byte/word transfer
Byte/word transfer
Byte/word transfer
Byte/word transfer
12 states (889 ns)
12 states (889 ns)
12 states (889 ns)
12 states (889 ns)
12 states (889 ns)
8 states (593 ns)
8 states (593 ns)
8 states (593 ns)
8 states (593 ns)
8 states (593 ns)
Execution time
4-byte transfer
4-byte transfer
4-byte transfer
4-byte transfer
4-byte transfer
(370 ns)
5 states
TMP91CW40
2008-09-19