TMP91xy40FG Toshiba, TMP91xy40FG Datasheet - Page 212

• Manufacturer Part Number: TMP91xy40FG
• Manufacturer: Toshiba

Specifications of TMP91xy40FG

• Package: LQFP100
• Rom Types(m=mask,p=otp, F=flash,e=eeprom): M/F
• Rom Combinations: 128
• Ram Combinations: 4
• Architecture: 16-bit CISC
• Usb/spi Channels: -
• Uart/sio Channels: 4
• I2c/sio Bus Channels: -
• (s)dram Controller: -
• Adc 10-bit Channel: 4
• Da Converter: -
• Timer 8-bit Channel: 4
• Timer 16-bit Channel: 3
• Pwm 8-bit Channels: -
• Pwm 16-bit Channels: -
• Cs/wait Controller: -
• Dual Clock: Y
• Number Of I/o Ports: 61
• Power Supply Voltage(v): 2.2 to 3.6

(2) Points of note
a.
b.
c.
d.
e.
f.
g.
h.
i.
However, the internal I/O continues to operate. Hence the watchdog timer continues to run.
Therefore be careful about the bus releasing time and set the detection timer of watchdog
timer.
reduce power consumption. When STOP mode is used, disable the resistor using the
program before the HALT instruction is executed.
the CPU (e.g., the transfer source address register (DMASn)).
operates), the internal Special timer for CLOCK operate. When necessary, stop the circuit
by setting RTCCR<RTCRUN> to “0”, before the HALT instructions is executed.
an external oscillator. As a result a time equivalent to the warm-up time elapses between
input of the release request and output of the system clock.
watchdog timer is not to be used, disable it.
AM0 and AM1 pins
EMU0 and EMU1
HALT mode (IDLE1)
Warm-up counter
Watchdog timer
AD converter
CPU (Micro DMA)
Undefined SFR
POP SR instruction
This pin is connected to the DVCC pin. Do not alter the level when the pin is active.
Open pins.
When the HALT instruction is executed in IDLE1 mode (in which only the oscillator
The warm-up counter operates when STOP mode is released, even if the system is using
The watchdog timer starts operation immediately after a reset is released. When the
When the bus is released, neither internal memory nor internal I/O can be accessed.
The string resistor between the VREFH and VREFL pins can be cut by a program so as to
Only the LDC cr, r and LDC r, cr instructions can be used to access the control registers in
The value of an undefined bit in an SFR is undefined when read.
Please execute the POP SR instruction during DI condition.
91CW40-210
TMP91CW40
2008-09-19