TMP91xy40FG Toshiba, TMP91xy40FG Datasheet - Page 24

• Manufacturer Part Number: TMP91xy40FG
• Manufacturer: Toshiba

Specifications of TMP91xy40FG

• Package: LQFP100
• Rom Types(m=mask,p=otp, F=flash,e=eeprom): M/F
• Rom Combinations: 128
• Ram Combinations: 4
• Architecture: 16-bit CISC
• Usb/spi Channels: -
• Uart/sio Channels: 4
• I2c/sio Bus Channels: -
• (s)dram Controller: -
• Adc 10-bit Channel: 4
• Da Converter: -
• Timer 8-bit Channel: 4
• Timer 16-bit Channel: 3
• Pwm 8-bit Channels: -
• Pwm 16-bit Channels: -
• Cs/wait Controller: -
• Dual Clock: Y
• Number Of I/o Ports: 61
• Power Supply Voltage(v): 2.2 to 3.6

Note 1: If the interrupt request level is greater than the mask level, an INT0 or INT1 interrupt signal which is programmed as
*1: The TMP91CW40 exits the HALT mode after the warm-up period timer expires.
♦: Execution resumes with the interrupt service routine.
◊: Execution resumes with the instruction immediately following the HALT instruction. (The interrupt is not serviced.)
×: Cannot be used to exit a HALT mode.
−: These combinations are not possible because nonmaskable interrupts are assigned the highest priority level (7).
Example of exiting a HALT mode
NMI
INTWD
INT0,INT1, KWI0 to KWI3
INTALM0 to INTALM4
INTRTC
INTTMR1 to INTTMR3,
INTTMR5 to INTTMR8
INTRX0 to INTRX3, INTTX0 to INTTX3
INTAD
level-sensitive must be held high until interrupt processing begins. Otherwise, the interrupt will not be serviced successfully.
RESET
Interrupt Masking
When using an edge-sensitive INT0 interrupt to exit IDLE1 mode
HALT mode
Address
FE8200H
FE8203H
FE8206H
FE8209H
FE820BH
FE820EH
FE820FH
INT0
Table 3.3.4 Wakeup Signaling Sources and Wakeup Operations
LD
LD
LD
EI
LD
HALT
LD
Note 1)
(P6FC), 01H
(IIMC), 00H
(INTE0AD), 06H
5
(SYSCR2), 28H
XX, XX
Programmable IDLE2
(Request level) ≥ (Mask level)
♦
♦
♦
♦
♦
♦
♦
♦
♦
Unmasked Interrupt
91CW40-22
;
;
;
;
;
;
IDLE1
Initializes the whole TMP91CW40.
♦
♦
♦
♦
×
×
×
×
×
Set INT0 interrupt to rising-edge sensitive.
Set P60 to INT0.
Set INT0 interrupt priority level to 6.
Set CPU interrupt priority level to 5.
Select IDLE1 mode.
Stop CPU.
STOP
♦
♦
×
×
×
×
×
×
×
*1
*1
Programmable IDLE2
INT0 interrupt service routine
(Request level) < (Mask level)
◊
◊
◊
RETI
−
−
×
×
×
×
Masked Interrupt
IDLE1
TMP91CW40
−
−
◊
◊
◊
×
×
×
×
2008-09-19
STOP
◊
−
−
×
×
×
×
×
×
*1