TMP91xy40FG Toshiba, TMP91xy40FG Datasheet - Page 118

• Manufacturer Part Number: TMP91xy40FG
• Manufacturer: Toshiba

Specifications of TMP91xy40FG

• Package: LQFP100
• Rom Types(m=mask,p=otp, F=flash,e=eeprom): M/F
• Rom Combinations: 128
• Ram Combinations: 4
• Architecture: 16-bit CISC
• Usb/spi Channels: -
• Uart/sio Channels: 4
• I2c/sio Bus Channels: -
• (s)dram Controller: -
• Adc 10-bit Channel: 4
• Da Converter: -
• Timer 8-bit Channel: 4
• Timer 16-bit Channel: 3
• Pwm 8-bit Channels: -
• Pwm 16-bit Channels: -
• Cs/wait Controller: -
• Dual Clock: Y
• Number Of I/o Ports: 61
• Power Supply Voltage(v): 2.2 to 3.6

(9) Transmit buffer
(10) Parity controller
(11) Error flags
7- and 8-bit UART modes. The SC0CR<EVEN> bit selects either even or odd parity.
the transmit buffer (SC0BUF). In 7-bit UART mode, the SC0BUF<TB7> bit holds the
parity bit. In 8-bit UART mode, the SC0MOD0<TB8> bit holds the parity bit. The
SC0CR<PE> and <EVEN> bits must be programmed prior to a write to the transmit
buffer.
parity when a character in receive buffer 1 is transferred to receive buffer 2 (SC0BUF) .
The received parity bit is compared to the SC0BUF<RB7> bit in 7-bit UART mode and
to the SC0CR<RB8> bit in 8-bit UART mode. If a character is received with incorrect
parity, the SC0CR<PERR> bit is set.
1.
on the TXD output, with the least-significant bit first, clocked by the transmit shift
clock TXDSFT from the transmit controller. When the transmit buffer is empty and
ready to be loaded with the next character, the INTT0 interrupt is generated to the
CPU.
received character for improved data reception reliability.
Once the CPU loads a character into the transmit buffer (SC0BUF), it is shifted out
For transmit operations, setting the SC0CR<PE> bit to 1 enales parity generation in
If enabled, the parity controller automatically generates parity for the character in
For receive operations, the parity controller automatically computes the expected
The SC1CR register has the following error flag bits that indicate the status of the
Overrun error <OERR>
receive buffer 1 when receive buffer 2 (SC0BUF) still contains a valid character.
(Receive interrupt routine)
An overrun error is reported if all bits of a new character are received into
The following shows an example processing flow when an overrun error occurs:
1) Read the receive buffer.
2) Read the error flags.
3) if <OERR> = 1
4) Other processing
then
a) Disable reception: Write 0 to <RXE>.
b) Wait until the current frame is completed.
c) Read the receive buffer.
d) Read the error flags.
e) Enable reception: Write 1 to <RXE>.
f) Request retransmission.
91CW40-116
TMP91CW40
2008-09-19