TMP91xy40FG Toshiba, TMP91xy40FG Datasheet - Page 113

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TMP91xy40FG

Manufacturer Part Number
TMP91xy40FG
Description
Manufacturer
Toshiba
Datasheet

Specifications of TMP91xy40FG

Package
LQFP100
Rom Types(m=mask,p=otp, F=flash,e=eeprom)
M/F
Rom Combinations
128
Ram Combinations
4
Architecture
16-bit CISC
Usb/spi Channels
-
Uart/sio Channels
4
I2c/sio Bus Channels
-
(s)dram Controller
-
Adc 10-bit Channel
4
Da Converter
-
Timer 8-bit Channel
4
Timer 16-bit Channel
3
Pwm 8-bit Channels
-
Pwm 16-bit Channels
-
Cs/wait Controller
-
Dual Clock
Y
Number Of I/o Ports
61
Power Supply Voltage(v)
2.2 to 3.6
Integral clock division (divide-by-N)
N + (16 − K)/16 clock division (UART mode only)
generator. When an external clock is used, the baud rate is determined as shown
below.
clock inputs and clocl divisor values.
Table 3.10.3 shows the UART baud rates obtained with various combinations of
* Clocking conditions:
* Clocking conditions:
The baud rate is determined as follows:
Baud rate =
= 12.288 × 10
Note:
The baud rate is determined as follows:
fc = 12.288 MHz
Input clock: φT2
Clock divisor N (BR0CR<BR0S3:0>) = 5
BR0CR<BR0ADDE> = 0
fc = 4.8 MHz
Input clock: φT0
N (BR0CR<BR0S3:0>) = 7
K (BR0ADD<BR0K3:0>) = 3
BR0CR<BR0ADDE> = 1
The SIO can use an external clock as a serial clock, bypassing the baud rate
= 4.8 × 10
Baud rate =
UART mode
I/O interface mode
Baud rate = external clock input ÷ 16
The external clock period must be greater than or equal to 4/fc.
Baud rate = external clock input
The external clock period must be greater than or equal to 16/fc.
Clearing the BR0CR<BR0ADDE> to 0 disables the N + (16 − K)/16 clock division function. At this
time, the BR0ADD<BR0K3:0> field is ignored.
=
6
÷ 4 ÷ ( 7 +
Baud rate generator input clock
Baud rate generator divisor
6
=
fc/16
÷ 16 ÷ 5 ÷ 16 = 9600 (bps)
5
Baud rate generator input clock
Baud rate generator divisor
7
+
System clock:
System clock:
÷
fc/4
91CW40-111
(16 − 3)
13
16
16
16
) ÷ 16 = 9600 (bps)
÷
16
High-speed (fc)
High-speed (fc)
÷ 16
÷ 16
TMP91CW40
2008-09-19

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