TMP91xy40FG Toshiba, TMP91xy40FG Datasheet - Page 37

• Manufacturer Part Number: TMP91xy40FG
• Manufacturer: Toshiba

Specifications of TMP91xy40FG

• Package: LQFP100
• Rom Types(m=mask,p=otp, F=flash,e=eeprom): M/F
• Rom Combinations: 128
• Ram Combinations: 4
• Architecture: 16-bit CISC
• Usb/spi Channels: -
• Uart/sio Channels: 4
• I2c/sio Bus Channels: -
• (s)dram Controller: -
• Adc 10-bit Channel: 4
• Da Converter: -
• Timer 8-bit Channel: 4
• Timer 16-bit Channel: 3
• Pwm 8-bit Channels: -
• Pwm 16-bit Channels: -
• Cs/wait Controller: -
• Dual Clock: Y
• Number Of I/o Ports: 61
• Power Supply Voltage(v): 2.2 to 3.6

3.4.3
Interrupt Controller
diagram shows the interrupt controller while the right-hand side shows the CPU’s
interrupt request signal circuit and halt wakeup circuit.
register and micro DMA start vector register. The interrupt request flag is used to latch an
interrupt request issued by peripherals.
(such as INTE0AD and INTE1ALM0) provided for each interrupt source. Six levels of
priority (1 to 6) can be set. An interrupt is disabled when its priority level is set to 0 or 7.
Nonmaskable interrupts (
more interrupts having the same priority level occur simutaneously, the CPU accepts
interrupts according to default priorities. Reading bits 3 and 7 of an interrupt priority
register obtains the status of the interrupt request flag, indicating whether an interrupt
request is present for the corresponding channel.
interrupts occuring simultaneously if any, and sends it priority level and vector address to
the CPU. The CPU compares that priority level with the contents of the interrupt mask
register, that is, the <IFF2:0> bits of the status register (SR). The CPU accepts the
interrupt if its priority level is higher than the register value. It then sets the <IFF2:0> bits
to the accepted interrupt level plus one, so that only interrupt requests having a priority
level higher than or equal to the register value can be accepted while the current interrupt
is handled. Upon completion of interrupt servicing (with the execution of the RETI
instruction), the <IFF2:0> bits are restored to the value before the interrupt occurred
which has been saved on the stack.
channels. Writing a start vector (see Table 3.4.1) to these registers enables the micro DMA
to start when the corresponding interrupt occurs. Note that the registers for setting micro
DMA parameters (such as DMAS and DMAD) must be set beforehand.
Figure 3.4.3 shows a block diagram of the interrupt circuit. The left-hand side of the
For each of the 25 interrupt channels there is an interrupt request flag, interrupt priority
This flag is cleared in the following cases:
Priority levels for individual interrupts can be specified using interrupt priority registers
The interrupt controller determines the interrupt with the highest priority among
The interrupt controller has registers for storing mirco DMA start vectors for four
•
•
•
•
•
Reset
The CPU accepts the interrupt and reads the vector for the interrupt.
An instruction that clears the interrupt is executed. (A DMA start vector is written
The CPU accepts a micro DMA request for the interrupt.
Micro DMA burst transfer for the interrupt completes.
to the INTCLR register.)
NMI
pin and watchdog timer) have a fixed level of 7. If two or
91CW40-35
TMP91CW40
2008-09-19