TMP91xy40FG Toshiba, TMP91xy40FG Datasheet - Page 129

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TMP91xy40FG

Manufacturer Part Number
TMP91xy40FG
Description
Manufacturer
Toshiba
Datasheet

Specifications of TMP91xy40FG

Package
LQFP100
Rom Types(m=mask,p=otp, F=flash,e=eeprom)
M/F
Rom Combinations
128
Ram Combinations
4
Architecture
16-bit CISC
Usb/spi Channels
-
Uart/sio Channels
4
I2c/sio Bus Channels
-
(s)dram Controller
-
Adc 10-bit Channel
4
Da Converter
-
Timer 8-bit Channel
4
Timer 16-bit Channel
3
Pwm 8-bit Channels
-
Pwm 16-bit Channels
-
Cs/wait Controller
-
Dual Clock
Y
Number Of I/o Ports
61
Power Supply Voltage(v)
2.2 to 3.6
(3) Mode 2 (8-bit UART mode)
Settings in the main routine
Example of interrupt routine processing
P9CR
SC0MOD0
SC0CR
BR0CR
INTES0
mode, the parity bit can be added to the transmitted character, and the receiver can
perform a parity check on incoming data. Parity can be enabled and disabled by
programming the SC0CR<PE> bit. When <PE> is set to 1 to enable parity, the
SC0CR<EVEN> bit selects even or odd parity.
Example: Receiving data with odd parity in 8-bit UART mode
X: Don’t care 、− : No change
Acc ← SC0CR AND 00011100
if Acc ← 0 then ERROR
Acc ← SC0BUF
Setting the SC0MOD0<SM1:0> field to 10 puts the SIO0 in 8-bit UART mode. In this
Start
← – – – – – – 0 –
← – 0 1 X 1 0 0 1
← X 0 1 X X X 0 0
← 0 0 0 1 0 1 0 1
← – – – – X 1 0 0
7 6 5 4 3 2 1 0
Bit0
* Clock conditions
1
Transfer direction (Transfer rate: 9600 bps at fc = 12.288 MHz)
2
91CW40-127
3
Check for errors.
Read received data.
System clock:
Configure the P91(RXD0) pin as an input.
Select 8-bit UART mode and enable the receiver.
Select odd parity.
Set the transfer rate to 9600 bps.
Enable the INTRX0 interrupt and set its interrupt level to 4.
4
5
6
7
parity Stop
High-speed (fc)
Odd
TMP91CW40
2008-09-19

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