TMP91xy40FG Toshiba, TMP91xy40FG Datasheet - Page 33

• Manufacturer Part Number: TMP91xy40FG
• Manufacturer: Toshiba

Specifications of TMP91xy40FG

• Package: LQFP100
• Rom Types(m=mask,p=otp, F=flash,e=eeprom): M/F
• Rom Combinations: 128
• Ram Combinations: 4
• Architecture: 16-bit CISC
• Usb/spi Channels: -
• Uart/sio Channels: 4
• I2c/sio Bus Channels: -
• (s)dram Controller: -
• Adc 10-bit Channel: 4
• Da Converter: -
• Timer 8-bit Channel: 4
• Timer 16-bit Channel: 3
• Pwm 8-bit Channels: -
• Pwm 16-bit Channels: -
• Cs/wait Controller: -
• Dual Clock: Y
• Number Of I/o Ports: 61
• Power Supply Voltage(v): 2.2 to 3.6

3.4.2
Micro DMA
feature. Interrupt requests specified with the micro DMA are assigned highest priority
levels among maskable interrupts regardless of the priority levels actually set.
using burst specification, described later.
requests are ignored and remain pending if the CPU executes the HALT instruction and
enters a standby state.
(1) Micro DMA operation
In addition to general interrupt servicing, the TMP91CW40 supports a micro DMA
The micro DMA consists of four channels so that continuous transfer can be performed
Because the micro DMA feature is realized in cooperation with the CPU, micro DMA
Note: If the priority level of micro DMA is set higher than that of other interrupts, CPU operates as follows.
micro DMA transfers data to the CPU assuming the highest priority level for a
maskable interrupt regardless of the priority level assigned to the interrupt source.
Micro DMA requests are not, however, accepted when <IFF2:0> = 7.
sources simultaneously.
assigned to that channel, performs a single data transfer (1 byte, 2 bytes, or 4 bytes)
from the source address to destination address, as specified with the control register,
and then decrements the transfer counter. If the decremented counter reaches zero,
the interrupt controller receives a request from the CPU and generates a micro DMA
transfer complete interrupt (INTTCn). Then the CPU clears the micro DMA start
vector register (DMAnV) to 0, thus disabling subsequent start of the micro DMA and
terminating micro DMA servicing. Even if the decremented counter does not reach
zero, the CPU terminates micro DMA servicing unless burst transfer is specified. In
this case, the interrupt controller does not generate a micro DMA transfer complete
interrupt (INTTCn).
for that interrupt to 0. If the priority level is set to 1 to 6 and this interrupt request is
generated before it is set for micro DMA transfer, the CPU will perform general
interrupt servicing.
servicing, set the priority level for that interrupt to a level less that those of all other
interrupt sources. Note that only edge-triggered interrupts can be used in such a way.
and default priorities, in the same way as other maskable interrupts.
smaller numbers have higher priorities, regardless of the respective interrupt
priority levels.
control register. The micro DMA can, however, handle only 16-Mbyte space because
there are only 24 address output lines.
If an interrupt specified with the micro DMA start vector register is requested, the
The micro DMA has four channels so that it can be specified for up to four interrupt
When the CPU accepts a micro DMA request, it clears the interrupt request flag
When using an interrupt source for both the micro DMA and general interrupt
A micro DMA transfer complete interrupt is serviced according to its priority level
If two or more micro DMA channels issue requests simultaneously, channels having
The transfer source and destination addresses are each specified using a 32-bit
When using an interrupt source only to start the micro DMA, set the priority level
In case INTxxx interrupt is generated first and then INTyyy interrupt is generated between
checking “Interrupt specified by micro DMA start vector” (in the Figure 3.4.1) and reading
interrupt vector with setting below. The vector shifts to that of INTyyy at the time.
This is because the priority level of INTyyy is higher than that of INTxxx.
In the interrupt routine, CPU reads the vector of INTyyy because cheking of micro DMA has
finished. And INTyyy is generated regardless of transfer counter of micro DMA.
INTxxx: level 1 without micro DMA
INTyyy: level 6 with micro DMA
91CW40-31
TMP91CW40
2008-09-19