TMP91xy40FG Toshiba, TMP91xy40FG Datasheet - Page 112

• Manufacturer Part Number: TMP91xy40FG
• Manufacturer: Toshiba

Specifications of TMP91xy40FG

• Package: LQFP100
• Rom Types(m=mask,p=otp, F=flash,e=eeprom): M/F
• Rom Combinations: 128
• Ram Combinations: 4
• Architecture: 16-bit CISC
• Usb/spi Channels: -
• Uart/sio Channels: 4
• I2c/sio Bus Channels: -
• (s)dram Controller: -
• Adc 10-bit Channel: 4
• Da Converter: -
• Timer 8-bit Channel: 4
• Timer 16-bit Channel: 3
• Pwm 8-bit Channels: -
• Pwm 16-bit Channels: -
• Cs/wait Controller: -
• Dual Clock: Y
• Number Of I/o Ports: 61
• Power Supply Voltage(v): 2.2 to 3.6

(2) Baud rate generator
the baud rate generator. The clock source for the baud rate generator can be selected
from the 6-bit prescaler outputs (φT0, φT2, φT8, φT32) through the programming of the
<BR0CK1:0> field in the BR0CR.
1, N+(16−K)/16, or 16. The clock divisor is programmed into the <BR0ADDE> and
<BR0S3:0> bits in the BR0CR and the <BR0K3:0> bits in the BR0ADD.
•
•
(1) When BR0CR<BR0ADDE> = 0
(2) When BR0CR<BR0ADDE> = 1
The frequency used to transmit and receive data through the SIO0 is derived from
The baud rate generator contains a clock divisor that can divide the selected clock by
・ UART mode
・ I/O interface mode
UART mode
I/O interface mode
The BR0CR<BR0ADDE> bit must be cleared to 0, so the baud rate generator input
clock is divided down by a value of N (1 to 16) programmed in the
BR0CR<BR0S3:0> field.
meaning or effect. The baud rate generator input clock is divided down by a value
of N (1 to 16) programmed in the BR0CR<BR0S3:0> field.
Note: Setting N to 1 or 16 disables the N + (16 − K)/16 clock division function. When N=1 or 16, the
The baud rate generator input clock is divided down according to a value of N (2
to 15) programmed in the BR0CR<BR0S3:0> field and a value of K (1 to 15)
programmed in the BR0ADD<BR0K3:0> field.
In I/O interface mode, the N + (16 − K)/16 clock division function cannot be used.
When the baud rate generator is used, the baud rate is calculated as follows:
When the <BR0ADDE> bit is cleared, the BR0ADD<BR0K3:0> field has no
Setting the <BR0ADDE> bit enables the N+ (16 − K)/16 clock division function.
Baud rate
Baud rate
BR0CR<BR0ADDE> bit must be cleared to 0.
=
=
Baud rate generator input clock
Baud rate generator divisor
Baud rate generator input clock
Baud rate generator divisor
91CW40-110
÷ 2
÷ 16
TMP91CW40
2008-09-19