TMP91xy40FG Toshiba, TMP91xy40FG Datasheet - Page 12

• Manufacturer Part Number: TMP91xy40FG
• Manufacturer: Toshiba

Specifications of TMP91xy40FG

• Package: LQFP100
• Rom Types(m=mask,p=otp, F=flash,e=eeprom): M/F
• Rom Combinations: 128
• Ram Combinations: 4
• Architecture: 16-bit CISC
• Usb/spi Channels: -
• Uart/sio Channels: 4
• I2c/sio Bus Channels: -
• (s)dram Controller: -
• Adc 10-bit Channel: 4
• Da Converter: -
• Timer 8-bit Channel: 4
• Timer 16-bit Channel: 3
• Pwm 8-bit Channels: -
• Pwm 16-bit Channels: -
• Cs/wait Controller: -
• Dual Clock: Y
• Number Of I/o Ports: 61
• Power Supply Voltage(v): 2.2 to 3.6

3.3
System Clock/Standby Control and Noise Reduction
minimize power consumption and noise. Single-clock mode (X1 and X2 pins only) and dual-clock
mode (X1, X2, XT1, and XT2 pins) are supported.
The TMP91CW40 incorporates clock gear, standby control and noise reduction circuits to
Figure 3.3.1 shows state transitions in each clock mode.
The clock frequency terms used in this document are defined as follows:
(Only oscillator active)
(Only oscillator active)
(Only oscillator active)
fc: Clock frequency supplied via the X1 and X2 pins
fs: Clock frequency supplied via the XT1 and XT2 pins
f
f
1 state: One period of f
FPH
SYS
発振
IDLE2 mode
IDLE1 mode
IDLE2 mode
IDLE1 mode
IDLE1 mode
IDLE2 mode
(I/O active)
(I/O active)
(I/O active)
: Clock frequency obtained by dividing f
: Clock frequency selected by SYSCR1<SYSCK>
動作
Figure 3.3.1 State Transitions in Each Operation Mode
動作
(a) State Transitions in Single-Clock Mode
Interrupt
Interrupt
(b) State Transitions in Dual-Clock Mode
Interrupt
Instruction
Instruction
Instruction
Instruction
Instruction
Instruction
Interrupt
Interrupt
Interrupt
SYS
91CW40-10
NORMAL mode
NORMAL mode
SLOW mode
Instruction
Reset
Reset
(f
(f
(f
(f C /2)
(fs/2)
C
C
C
/2)
/2)
/2)
Reset released
Reset released
Instruction
FPH
Instruction
Interrupt
Interrupt
by two
Instruction
(Whole chip halted)
(Whole chip halted)
STOP mode
STOP mode
TMP91CW40
2008-09-19