TMP91xy40FG Toshiba, TMP91xy40FG Datasheet - Page 54

• Manufacturer Part Number: TMP91xy40FG
• Manufacturer: Toshiba

Specifications of TMP91xy40FG

• Package: LQFP100
• Rom Types(m=mask,p=otp, F=flash,e=eeprom): M/F
• Rom Combinations: 128
• Ram Combinations: 4
• Architecture: 16-bit CISC
• Usb/spi Channels: -
• Uart/sio Channels: 4
• I2c/sio Bus Channels: -
• (s)dram Controller: -
• Adc 10-bit Channel: 4
• Da Converter: -
• Timer 8-bit Channel: 4
• Timer 16-bit Channel: 3
• Pwm 8-bit Channels: -
• Pwm 16-bit Channels: -
• Cs/wait Controller: -
• Dual Clock: Y
• Number Of I/o Ports: 61
• Power Supply Voltage(v): 2.2 to 3.6

P7
(0013H)
P7CR
(0016H)
P7FC
(0017H)
P7FC2
(002DH)
Note 1: The P7CR, P7FC and P7FC2 do not support read-modify-write
Note 2: The P70 to P75 (ECNT1 to ECNT3, ECIN1 to ECIN3) pins do not
Bit symbol
Read/Write
After reset
Bit symbol
Read/Write
After reset
Function
Bit symbol
Read/Write
After reset
Function
Bit symbol
Read/Write
After reset
Function
operation.
have a register bit for selecting the port or timer function. The input
to these pins is always directed to 16-bit timers 1 to 3 even when
they are used as general-purpose input pins.
7
7
7
7
6
6
6
6
Figure 3.5.8 Port 7 Registers
P75C
Port 7 Function Register 2
P75
Port 7 Function Register
Port 7 Control Register
5
5
5
5
0
91CW40-52
Data from external port (Output latch register is reset to 0.)
Port 7 Register
P74C
P74
4
4
4
4
0
0: Input
P73C
P73
0
3
3
3
3
R/W
W
0: Port
1: DVO
0: Port/
1:
1: Output
P72F2
MLDALM
DVO
P72C
P72F
P72
0
W
W
2
2
2
2
0
0
P72 DVO output setting
P7FC<P72F>
P7FC2<P72F2>
P7CR<P72C>
Port 7 input/output setting
P72 MLDALM output setting
P7FC2<P72F2>
P7CR<P72C>
P71C
0 Input
1 Output
P71
0
1
1
1
1
TMP91CW40
P70C
P70
2008-09-19
0
0
0
0
0
1
0
1
1
1