TMP91xy40FG Toshiba, TMP91xy40FG Datasheet - Page 128

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TMP91xy40FG

Manufacturer Part Number
TMP91xy40FG
Description
Manufacturer
Toshiba
Datasheet

Specifications of TMP91xy40FG

Package
LQFP100
Rom Types(m=mask,p=otp, F=flash,e=eeprom)
M/F
Rom Combinations
128
Ram Combinations
4
Architecture
16-bit CISC
Usb/spi Channels
-
Uart/sio Channels
4
I2c/sio Bus Channels
-
(s)dram Controller
-
Adc 10-bit Channel
4
Da Converter
-
Timer 8-bit Channel
4
Timer 16-bit Channel
3
Pwm 8-bit Channels
-
Pwm 16-bit Channels
-
Cs/wait Controller
-
Dual Clock
Y
Number Of I/o Ports
61
Power Supply Voltage(v)
2.2 to 3.6
(2) Mode 1 (7-bit UART mode)
mode, the parity bit can be added to the transmitted character, and the receiver can
perform a parity check on incoming data. Parity can be enabled and disabled by
programming the SC0CR<PE> bit. When <PE> is set to 1 to enable parity, the
SC0CR<EVEN> bit selects even or odd parity.
Example: Transmitting data with even parity in 7-bit UART mode
P9CR
P9FC
SC0MOD0 ← X 0 − X 0 1 0 1
SC0CR
BR0CR
INTES0
SC0BUF
X: Don’t care 、
Setting the SC0MOD0<SM1:0> field to 01 puts the SIO0 in 7-bit UART mode. In this
← − − − − − − − 1
← − − − − − − − 1
← X 1 1 X X X 0 0
← 0 0 1 0 0 1 0 1
← X 1 0 0 − − − −
← * * * * * * * *
Start
7 6 5 4 3 2 1 0
: No change
Bit0
* Clock conditions
Transfer direction (Transfer rate: 2400 bps at fc = 12.288 MHz)
1
91CW40-126
2
3
Configure the P90 pin as TXD0.
Select 7-bit UART mode.
Select even parity.
Set the transfer rate to 2400 bps.
Enable the INTTX0 interrupt and set its interrupt level to 4.
Load the transmit buffer with transmit data.
System clock:
4
5
6
parity Stop
Even
High-speed (fc)
TMP91CW40
2008-09-19

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