TMP91xy40FG Toshiba, TMP91xy40FG Datasheet - Page 141

• Manufacturer Part Number: TMP91xy40FG
• Manufacturer: Toshiba

Specifications of TMP91xy40FG

• Package: LQFP100
• Rom Types(m=mask,p=otp, F=flash,e=eeprom): M/F
• Rom Combinations: 128
• Ram Combinations: 4
• Architecture: 16-bit CISC
• Usb/spi Channels: -
• Uart/sio Channels: 4
• I2c/sio Bus Channels: -
• (s)dram Controller: -
• Adc 10-bit Channel: 4
• Da Converter: -
• Timer 8-bit Channel: 4
• Timer 16-bit Channel: 3
• Pwm 8-bit Channels: -
• Pwm 16-bit Channels: -
• Cs/wait Controller: -
• Dual Clock: Y
• Number Of I/o Ports: 61
• Power Supply Voltage(v): 2.2 to 3.6

(2) Blanking
Note: During reset, COM outputs are initialized to GND level, but SEG outputs (SEG0 to SEG7) and port/SEG
GND level and the SEG pins are placed in a high-impedance state.
STOP mode is exited, the <EDSP> bit need be set to 1 to display data on the LCD
again.
When the <EDSP> bit in the LCDCR is cleared to 0, the COM pins are driven to
When the TMP91CW40 enters STOP mode, the <EDSP> bit is cleared to 0. After
The following shows a programming example for fixing the SEG pins to low level.
LD
LD
LD
LD
LD
LD
LD
LD
LD
LD
LD
LD
LD
LD
multiplexed pins (P0, P1, P2 and PB ports) are placed in a high-impedance state. Therefore, if a
considerably long external reset input occurs, the LCD may not be displayed properly.
(P2CR),0FFH
(P1CR),0FFH
(P0CR),0FFH
(PBCR),0FFH
(P2),00H
(P1),00H
(P0),00H
(PB),00H
(LCDSW1),00H
(LCDSW2),00H
(LCDSW3),00H
(LCDSW4),00H
(LCDCR),00H
(LCDCR2),20H
91CW40-139
<MSEG07>=1, setting SEG0 to SEG 7 for low output
<EDSP>=0
Configure ports for low output.
Configure port/SEG multiplexed pins as port pins.
The SEG pins become ports fixed to low level.
TMP91CW40
2008-09-19