TMP91xy40FG Toshiba, TMP91xy40FG Datasheet - Page 192

• Manufacturer Part Number: TMP91xy40FG
• Manufacturer: Toshiba

Specifications of TMP91xy40FG

• Package: LQFP100
• Rom Types(m=mask,p=otp, F=flash,e=eeprom): M/F
• Rom Combinations: 128
• Ram Combinations: 4
• Architecture: 16-bit CISC
• Usb/spi Channels: -
• Uart/sio Channels: 4
• I2c/sio Bus Channels: -
• (s)dram Controller: -
• Adc 10-bit Channel: 4
• Da Converter: -
• Timer 8-bit Channel: 4
• Timer 16-bit Channel: 3
• Pwm 8-bit Channels: -
• Pwm 16-bit Channels: -
• Cs/wait Controller: -
• Dual Clock: Y
• Number Of I/o Ports: 61
• Power Supply Voltage(v): 2.2 to 3.6

3.17.2
Operational Description
WDT counter
WDT interrupt
WDT clear
(via software)
WDT counter
WDT interrupt
Internal reset
out. The watchdog timer allows the user to program the time-out period in the
<WDTP1:0> field in the WDMOD register. While the watchdog timer is enabled, it can be
cleared to 0 by software at any time by writing a special clear code. If the CPU loses
control of the system and fails to execute an instruction to clear the counter before it
reaches the time-out time due to noise or other causes, the watchdog timer generates an
INTWD interrupt. In response to the interrupt, the CPU jumps to a system recovery
routine to regain control of the system.
watchdog timer is disabled. Program the <I2WDT> bit as necessary before placing the
TMP91CW40 in IDLE2 mode.
The binary counter can output f
WDMOD<WDTP1:0>. When the watchdog timer counter overflows, a watchdog timer
interrupt is generated as shown in Figure 3.17.2.
this case, a reset operation takes 22 to 29 states (1.63 to 2.15 μs when fc = 27 MHz) as
shown in Figure 3.17.3. After a reset, the system clock f
The watchdog timer contains a 22-stage binary counter clocked by the system clock f
The watchdog timer is a kind of timer that generates an interrupt request if it times
The watchdog timer begins counting immediately after reset.
The watchdog timer halted in IDLE1 or STOP mode.
In IDLE2 mode, the <I2WDT> bit in the WDMOD determines whether or not the
It is also possible to reset the system when the watchdog timer counter overflows. In
n
n
Figure 3.17.2 Normal Operation
22 to 29 states (1.63 to 2.15 μs when fc = 27MHz)
Figure 3.17.3 Reset Operation
Overflow
91CW40-190
Overflow
SYS
/2
15
, f
SYS
/2
17
, f
Write clear code
SYS
/2
19
SYS
or f
(1 cycle = 1 state) is fc/2.
SYS
/2
21
, which is selected by
TMP91CW40
2008-09-19
0
SYS.