TMP91xy40FG Toshiba, TMP91xy40FG Datasheet - Page 41

• Manufacturer Part Number: TMP91xy40FG
• Manufacturer: Toshiba

Specifications of TMP91xy40FG

• Package: LQFP100
• Rom Types(m=mask,p=otp, F=flash,e=eeprom): M/F
• Rom Combinations: 128
• Ram Combinations: 4
• Architecture: 16-bit CISC
• Usb/spi Channels: -
• Uart/sio Channels: 4
• I2c/sio Bus Channels: -
• (s)dram Controller: -
• Adc 10-bit Channel: 4
• Da Converter: -
• Timer 8-bit Channel: 4
• Timer 16-bit Channel: 3
• Pwm 8-bit Channels: -
• Pwm 16-bit Channels: -
• Cs/wait Controller: -
• Dual Clock: Y
• Number Of I/o Ports: 61
• Power Supply Voltage(v): 2.2 to 3.6

Note: When INT1 is is set to be level-sensitive, the key-on wakeup function must be disabled.
INTCLR
Symbol
INT1 sensitivity
INT0 sensitivity
Symbol
NMI
IIMC
0
1
0
1
0
1
rising edge enable
Edge-triggered
Level-sensitive
Edge-triggered
Level-sensitive
INT request occurs at falling edge only
INT request occurs at rising/falling edge
Interrupt
input
control
Interrupt
clear
control
Name
Name
(2) External interrupt control
(3) Interrupt request flag clear register
Table 3.4.1) to the INTCLR register.
operation after execution of the DI instruction.
An interrupt request flag can be cleared by writing a micro DMA start vector (see
For example, the INT0 interrupt flag can be cleared by the following register
INTCLR ← 0AH
are prohibited)
modify-write
instructions
prohibited)
modify-write
instructions
Address
Address
(Read-
(Read-
8CH
88H
are
7
−
0
7
Always write “0”.
Clear the INT0 interrupt request flag
6
6
−
0
91CW40-39
Writing a DMA start vector clears the corresponding interrupt request flag.
CLRV5
5
−
0
5
0
INT1 edge
polarity
0: Rising
1: Falling
I1EDGE
CLRV4
4
0
4
0
W
INT1
sensitivity
0: Edge
1: Level
CLRV3
I1LE
3
0
3
0
W
INT0 edge
polarity
0: Rising
1: Falling
I0EDGE
CLRV2
2
0
2
0
INT0
sensitivity
0: Edge
1: Level
CLRV1
I0LE
1
TMP91CW40
1
0
0
2008-09-19
1: Also
triggered by
edge
NMI rising
NMIREE
CLRV0
0
0
0
0