TMP91xy40FG Toshiba, TMP91xy40FG Datasheet - Page 126

• Manufacturer Part Number: TMP91xy40FG
• Manufacturer: Toshiba

Specifications of TMP91xy40FG

• Package: LQFP100
• Rom Types(m=mask,p=otp, F=flash,e=eeprom): M/F
• Rom Combinations: 128
• Ram Combinations: 4
• Architecture: 16-bit CISC
• Usb/spi Channels: -
• Uart/sio Channels: 4
• I2c/sio Bus Channels: -
• (s)dram Controller: -
• Adc 10-bit Channel: 4
• Da Converter: -
• Timer 8-bit Channel: 4
• Timer 16-bit Channel: 3
• Pwm 8-bit Channels: -
• Pwm 16-bit Channels: -
• Cs/wait Controller: -
• Dual Clock: Y
• Number Of I/o Ports: 61
• Power Supply Voltage(v): 2.2 to 3.6

<IRX0C>
(INTRX0
interrupt request)
RXD0
SCLK0 output
(<SCLKS>=0
Rising edge mode)
SCLK0 output
(<SCLKS>=1
Falling edge mode)
(INTRX0 interrupt request)
SCLK0 input
(<SCLKS> = 0:
rising edge mode)
SCLK0 input
(<SCLKS> = 1:
falling edge mode)
<IRX0C>
RXD0
b.
Figure 3.10.19 Receive Operation in I/O Interface Mode (SCLK0 input mode)
Figure 3.10.18 Receive Operation in I/O Interface Mode (SCLK output mode)
Receive operations
clearing the receive-done interrupt flag (INTES0<IRX0C>), the synchronization clock
is driven out from the SCLK pin to shift the next character into receive buffer 1. When
a whole 8-bit character has been loaded into receive buffer 1, it is transferred to receive
buffer 2 (SC0BUF), and the INTES0<IRX0C> flag is set to 1, generating the INTRX0
interrupt.
the receive-done interrupt flag (INTES0<IRX0C>), before the SCLK input is activated
to shift the next character into receive buffer 1. When a whole 8-bit character has been
loaded into receive buffer 1, it is transferred to receive buffer 2 (SC0BUF), and the
INTES0<IRX0C> flag is set to 1 again, generating the INTRX0 interrupt.
Note:
In SCLK output mode, each time the CPU picks up a character in receive buffer 2
The SCLK output is initiated by setting the SC0MOD0<RXE> bit to 1.
In SCLK input mode, the CPU must pick up a character in receive buffer 2, clearing
Regardless of whether SCLK is in input mode or output mode, the receiver must be enabled by setting the
SC0MOD0<RXE> bit to 1 in order to perform receive operations.
Bit0
Bit0
91CW40-124
Bit1
Bit1
Bit5
Bit6
Bit6
Bit7
Bit7
TMP91CW40
2008-09-19