TMP91xy40FG Toshiba, TMP91xy40FG Datasheet - Page 78

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TMP91xy40FG

Manufacturer Part Number
TMP91xy40FG
Description
Manufacturer
Toshiba
Datasheet

Specifications of TMP91xy40FG

Package
LQFP100
Rom Types(m=mask,p=otp, F=flash,e=eeprom)
M/F
Rom Combinations
128
Ram Combinations
4
Architecture
16-bit CISC
Usb/spi Channels
-
Uart/sio Channels
4
I2c/sio Bus Channels
-
(s)dram Controller
-
Adc 10-bit Channel
4
Da Converter
-
Timer 8-bit Channel
4
Timer 16-bit Channel
3
Pwm 8-bit Channels
-
Pwm 16-bit Channels
-
Cs/wait Controller
-
Dual Clock
Y
Number Of I/o Ports
61
Power Supply Voltage(v)
2.2 to 3.6
Source clock
Counter
TREG1A
INTTMR1 interrupt
3.8.3
Functional Description
TC1SEL = 0
fc/2
fc/2
fc/2
fc/2
fc/2
(1) Timer mode
23
13
11
7
3
The timer/counter 1 has the following four operating modes:
0
[Hz]
When a match between the counter value and the TREG1A register value is detected,
an INTTMR1 interrupt is generated and the counter is cleared. The counter continues
counting up after it has been cleared.
Source Clock
In the timer mode, the counter counts up on the rising edge of the internal clock.
Command start
n
Table 3.8.1 Timer/Counter 1 Source Clock (Internal Clock)
TC1SEL = 1
fs/2
fs/2
fs/2
15
5
3
1
[Hz]
Figure 3.8.4 Timer Mode Timing Chart
2
3
fc = 27 MHz
303.41 μs
75.85 μs
4.74 μs
0.31 s
0.3 μs
4
91CW40-76
Resolution
Match detect
fs = 32.768 kHz
0.98 ms
244 μs
n − 1 n 0
1s
Counter clear
fc = 27 MHz
1
310.69 ms
19.42 ms
19.88 s
5.66 h
4.97 s
Maximum Setting Time
2
3
fs = 32.768 kHz
1.07 min
4
18.2 h
16 s
5
TMP91CW40
2008-09-19
6

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