TMP91xy40FG Toshiba, TMP91xy40FG Datasheet - Page 183

• Manufacturer Part Number: TMP91xy40FG
• Manufacturer: Toshiba

Specifications of TMP91xy40FG

• Package: LQFP100
• Rom Types(m=mask,p=otp, F=flash,e=eeprom): M/F
• Rom Combinations: 128
• Ram Combinations: 4
• Architecture: 16-bit CISC
• Usb/spi Channels: -
• Uart/sio Channels: 4
• I2c/sio Bus Channels: -
• (s)dram Controller: -
• Adc 10-bit Channel: 4
• Da Converter: -
• Timer 8-bit Channel: 4
• Timer 16-bit Channel: 3
• Pwm 8-bit Channels: -
• Pwm 16-bit Channels: -
• Cs/wait Controller: -
• Dual Clock: Y
• Number Of I/o Ports: 61
• Power Supply Voltage(v): 2.2 to 3.6

ADMOD1
(02B1H)
Note: The AN3 pin is shared with the
Bit symbol
Read/Write
After reset
Function
enabled (i.e., ADMOD1<ADTRGE> = 1 ), the <ADCH2:0> field must not be set to 011.
VREF
control
0: OFF
1: ON
VREFON
R/W
7
0
ADC
operation in
IDLE2 mode
0: Stop
1: Operation
Figure 3.16.3 AD Conversion Registers (2)
I2AD
R/W
6
0
ADTRG
AD Mode Control Register 1
5
<ADCH2:0>
91CW40-181
pin. Therefore, when the external conversion trigger input (
000
001
010
011 (Note)
100
101
110
111
4
<SCAN>
External
conversion
trigger
0: Disable
1: Enable
ADTRGE
Analog input channel select
AD conversion start by external trigger
(
AD converter operation in IDLE2 mode
Reference voltage for AD converter
Set <VREFON> to 1 before setting
ADMOD0<ADS> to 1 to start a conversion.
3
0
0
1
0
1
0
1
ADTRG
Fixed-Channel
Must not be selected.
Disable
Enable
Stop
Operation
OFF
ON
Mode
AN0
AN1
AN2
AN3
0
Analog input channel select
input)
ADCH2
2
0
R/W
AN0
AN0 → AN1
AN0 → AN1 → AN2
AN0 → AN1 → AN2 → AN3
ADCH1
1
0
Channel Scan
Mode
1
ADCH0
TMP91CW40
0
0
2008-09-19
ADTRG
) is