TMP91xy40FG Toshiba, TMP91xy40FG Datasheet - Page 83

• Manufacturer Part Number: TMP91xy40FG
• Manufacturer: Toshiba

Specifications of TMP91xy40FG

• Package: LQFP100
• Rom Types(m=mask,p=otp, F=flash,e=eeprom): M/F
• Rom Combinations: 128
• Ram Combinations: 4
• Architecture: 16-bit CISC
• Usb/spi Channels: -
• Uart/sio Channels: 4
• I2c/sio Bus Channels: -
• (s)dram Controller: -
• Adc 10-bit Channel: 4
• Da Converter: -
• Timer 8-bit Channel: 4
• Timer 16-bit Channel: 3
• Pwm 8-bit Channels: -
• Pwm 16-bit Channels: -
• Cs/wait Controller: -
• Dual Clock: Y
• Number Of I/o Ports: 61
• Power Supply Voltage(v): 2.2 to 3.6

The Ta and Tb periods are represented by the following
equations:
Table 3.8.2 at the right shows the Ta and Tb times when fs =
32.768 kHz.
The Ta period is set by the upper 4 bits (bits 7 to 4) of the
TREG1B and the Tb period by the lower 4 bits (bits 3 to 0).
When (TC1CR2<WGPSCK> = 10):
(16 − n) × 2
(16 − n) × 2
(4) Frequency measurement mode
14
6
/fs [s]
/fc [s]
pin input pulse. (In this mode, TC1CR1<TC1CK> should be set to external clock.) The
counter counts up at the rising edge of the input pulse while the window gate pulse
selected by TC1CR2<SGP> is at high level. An INTTMR1 interrupt is generated at the
falling edge or at both the rising and falling edges of the window gate pulse, as
programmed in TC1CR2<SGEDG>. To use the ECNT1 pin input as the window gate
pulse, set TC1CR2<SGP> to 00. The counter value (TREG1A) should be read out in the
interrupt service routine while the counter is stopped (i.e., the window gate pulse is at
low level). Then, the counter should be cleared by using TC1CR<TC1C>. If the counter
is not cleared, it resumes counting up from the current value when counting is started
again. The window gate pulse state can be monitored by TC1SR<HECF>. Whether or
not an overflow occurred in the binary counter can be monitored by TC1SR<HEOVF>.
The overflow flag state is retained until the counter is cleared.
•
Ta
The frequency measurement mode is used to measure the frequency of the ECIN1
The internal window gate pulse, when selected, is set as explained below.
The internal window gate pulse is comprised of a high level period (Ta) in which
counting is performed and a low level period (Tb) in which counting is stopped.
The Ta and Tb periods can be programmed independently in the TREG1B register.
One cycle of the window gate pulse is defined as “Ta + Tb”.
Note 1:
Note 2:
or
Tb
Since the internal window gate pulse is generated in synchronization with the internal divider, a
delay of up to one source clock (WGPSCK) period may occur immediately after the timer is
started.
The window gate pulse must be programmed while the timer is stopped.
Figure 3.8.7 Window Gate Pulse Times
91CW40-81
Value n
0
1
2
3
4
5
6
7
(TC1CR2<WGPSCK> = 10, fs = 32.768 kHz)
Table 3.8.2 Ta and Tb Times
31.25 ms
29.30 ms
27.34 ms
25.39 ms
23.44 ms
21.48 ms
19.53 ms
17.58 ms
Time
Value n
C
D
A
B
E
F
8
9
TMP91CW40
2008-09-19
15.63 ms
13.67 ms
11.72 ms
9.77 ms
7.81 ms
5.86 ms
3.91 ms
1.95 ms
Time