TMP91xy40FG Toshiba, TMP91xy40FG Datasheet - Page 14

• Manufacturer Part Number: TMP91xy40FG
• Manufacturer: Toshiba

Specifications of TMP91xy40FG

• Package: LQFP100
• Rom Types(m=mask,p=otp, F=flash,e=eeprom): M/F
• Rom Combinations: 128
• Ram Combinations: 4
• Architecture: 16-bit CISC
• Usb/spi Channels: -
• Uart/sio Channels: 4
• I2c/sio Bus Channels: -
• (s)dram Controller: -
• Adc 10-bit Channel: 4
• Da Converter: -
• Timer 8-bit Channel: 4
• Timer 16-bit Channel: 3
• Pwm 8-bit Channels: -
• Pwm 16-bit Channels: -
• Cs/wait Controller: -
• Dual Clock: Y
• Number Of I/o Ports: 61
• Power Supply Voltage(v): 2.2 to 3.6

SYSCR2
SYSCR3
(00E2H)
(00E5H)
SYSCR1
SYSCR0
(00E1H)
(00E0H)
3.3.2
Note: Bits 7 to 4 of the SYSCR1 and bits 7 and 1 of the SYSCR2 are read as undefined.
Bit symbol
Read/Write
After reset
Function
Bit symbol
Read/Write
After reset
Function
Bit symbol
Read/Write
After reset
Function
Bit symbol
Read/Write
After reset
Function
SFRs
High-
frequency
oscillator
0: Stop
1: Active
XEN
7
1
Low-
frequency
oscillator
0: Stop
1: Active
Always write
0.
XTEN
R/W
Figure 3.3.3 SFRs for the System Clock
6
0
−
0
High-
frequency
oscillator
after release
of STOP
mode
0: Stop
1: Active
Oscillator warm-up time
00: Reserved
01: 2
10: 2
11: 2
WUPTM1
RXEN
R/W
8
14
16
5
1
1
/input frequency
/input frequency
/input frequency
91CW40-12
Low-
frequency
oscillator
after release
of STOP
mode
0: Stop
1: Active
WUPTM0
RXTEN
R/W
4
0
0
R/W
Clock
selection
after release
of STOP
mode
0: High-
frequency
1: Low-
frequency
System
clock
selection
0: High-
frequency
(fc)
1: Low-
frequency
(fs)
HALT mode selection
00: Reserved
01: STOP mode
10: IDLE1 mode
11: IDLE2 mode
RSYSCK
HALTM1
SYSCK
R/W
3
0
0
1
Warm-up
timer (WUP)
control
0 write:
1 write:
0 read:
1 read:
HALTM0
WUEF
Don’t
care
Start
WUP
WUP
finished
WUP
counting
R/W
2
0
−
0
1
R/W
Always write 000.
1
−
0
−
0
Always write 00.
1: Pins are
LCD clock
0: fc
1: fs
LCDCKMOD
driven in
STOP
mode.
TMP91CW40
DRVE
R/W
R/W
0
2008-09-19
−
0
−
0
0
0