AT32UC3L0256 Atmel Corporation, AT32UC3L0256 Datasheet - Page 75

• Manufacturer Part Number: AT32UC3L0256
• Manufacturer: Atmel Corporation

Specifications of AT32UC3L0256

• Flash (kbytes): 256 Kbytes
• Pin Count: 48
• Max. Operating Frequency: 50 MHz
• Cpu: 32-bit AVR
• # Of Touch Channels: 17
• Hardware Qtouch Acquisition: Yes
• Max I/o Pins: 36
• Ext Interrupts: 36
• Usb Speed: No
• Usb Interface: No
• Spi: 5
• Twi (i2c): 2
• Uart: 4
• Lin: 4
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 8
• Adc Resolution (bits): 12
• Adc Speed (ksps): 460
• Analog Comparators: 8
• Resistive Touch Screen: No
• Temp. Sensor: Yes
• Crypto Engine: No
• Sram (kbytes): 16
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: Yes
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.62 to 3.6
• Operating Voltage (vcc): 1.62 to 3.6
• Fpu: No
• Mpu / Mmu: Yes / No
• Timers: 6
• Output Compare Channels: 18
• Input Capture Channels: 12
• Pwm Channels: 35
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

7.8
32145A–12/2011
Module Configuration
The specific configuration for each PDCA instance is listed in the following tables.The module
bus clocks listed here are connected to the system bus clocks. Please refer to the Power Man-
ager chapter for details.
Table 7-6.
Table 7-7.
Table 7-8.
The PDCA and the peripheral modules communicate through a set of handshake signals. The
following table defines the valid settings for the Peripheral Identifier (PID) in the PDCA Periph-
eral Select Register (PSR). The direction is specified as observed from the memory, so RX
means transfers from peripheral to memory, and TX means from memory to peripheral.
Table 7-9.
Feature
Number of channels
Number of performance monitors
Clock Name
CLK_PDCA_HSB
CLK_PDCA_PB
Register
PSR CH 0
PSR CH 1
PSR CH 2
PSR CH 3
PSR CH 4
PSR CH 5
PSR CH 6
PSR CH 7
PSR CH 8
PSR CH 9
PSR CH 10
PSR CH 11
VERSION
PID
0
1
2
PDCA Configuration
PDCA Clocks
Register Reset Values
Peripheral Identity Values
Direction
RX
RX
RX
Peripheral Instance
USART0
USART1
USART2
Reset Value
0
1
2
3
4
5
6
7
8
9
10
11
123
PDCA
12
1
Description
Clock for the PDCA HSB interface
Clock for the PDCA PB interface
AT32UC3L0128/256
Peripheral Register
RHR
RHR
RHR
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