AT32UC3L0256 Atmel Corporation, AT32UC3L0256 Datasheet - Page 199

• Manufacturer Part Number: AT32UC3L0256
• Manufacturer: Atmel Corporation

Specifications of AT32UC3L0256

• Flash (kbytes): 256 Kbytes
• Pin Count: 48
• Max. Operating Frequency: 50 MHz
• Cpu: 32-bit AVR
• # Of Touch Channels: 17
• Hardware Qtouch Acquisition: Yes
• Max I/o Pins: 36
• Ext Interrupts: 36
• Usb Speed: No
• Usb Interface: No
• Spi: 5
• Twi (i2c): 2
• Uart: 4
• Lin: 4
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 8
• Adc Resolution (bits): 12
• Adc Speed (ksps): 460
• Analog Comparators: 8
• Resistive Touch Screen: No
• Temp. Sensor: Yes
• Crypto Engine: No
• Sram (kbytes): 16
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: Yes
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.62 to 3.6
• Operating Voltage (vcc): 1.62 to 3.6
• Fpu: No
• Mpu / Mmu: Yes / No
• Timers: 6
• Output Compare Channels: 18
• Input Capture Channels: 12
• Pwm Channels: 35
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

13.5.8.3
13.5.8.4
13.5.8.5
32145A–12/2011
Factory calibration
POR33 control
POR18 control
After a Power-on Reset (POR) the VREGCR.CALIB field is loaded with a factory defined calibra-
tion value. This value is chosen so that the normal output voltage of the regulator after a power-
up is 1.8V.
Although it is not recommended to override default factory settings, it is still possible to override
these default values by writing to VREGCR.CALIB.
If the Flash Calibration Done bit in VREGCR (VREGCR.FCD) is zero, the flash calibration will be
redone after any reset, and the VREGCR.FCD bit will be set before program execution starts in
the CPU. If VREGCR.FCD is one, the flash calibration will only be redone after a POR.
VREGCR includes control bits for the Power-on Reset 3.3V (POR33) detector that monitors the
internal regulator supply voltage. The POR33 detector is enabled by default but can be disabled
by software to reduce power consumption. The 3.3V Supply Monitor (SM33) can then be used to
monitor the regulator power supply.
T h e P O R 3 3 d e t e c t o r i s d i s a b l e d b y w r i t i n g a z e r o t o t h e P O R 3 3 E n a b l e b i t
(VREGCR.POR33EN). Because of internal synchronisation, the POR33 detector is not immedi-
ately enabled or disabled. The actual state of the POR33 detector can be read from the POR33
Status bit (VREGCR.POR33STATUS).
The 32kHz RC oscillator (RC32K) must be enabled before disabling the POR33 detector. Once
the POR33 detector has been disabled, the RC32K oscillator can be disabled again.
To avoid spurious resets, it is mandatory to mask the Power-on Reset when enabling or dis-
abling the POR33 detector. The Power-on Reset generated by the POR33 detector can be
ignored by writing a one to the POR33 Mask bit (VREGCR.POR33MASK). Because of internal
synchronization, the masking is not immediately effective, so software should wait for the
VREGCR.POR33MASK to read as a one before assuming the masking is effective.
The output of the POR33 detector is zero if the internal regulator supply voltage is below the
POR33 power-on threshold level, and one if the internal regulator supply voltage is above the
POR33 power-on threshold level. This output (before masking) can be read from the POR33
Value bit (VREGCR.POR33VALUE).
VREGCR includes control bits for the Power-on Reset 1.8V (POR18) detector that monitors the
VDDCORE voltage. The POR18 detector is enabled by default but can be disabled by software
to reduce power consumption.
T h e P O R 1 8 d e t e c t o r i s d i s a b l e d b y w r i t i n g a z e r o t o t h e P O R 1 8 E n a b l e b i t
(VREGCR.POR18EN). Because of internal synchronization, the POR18 detector is not immedi-
ately enabled or disabled. The actual state of the POR18 detector can be read from the POR18
Status bit (VREGCR.POR18STATUS).
Please note that the POR18 detector cannot be disabled while the JTAG or aWire debug inter-
face is used. Writing a zero to VREGCR.POR18EN bit will have no effect.
To avoid spurious resets, it is mandatory to mask the Power-on Reset when enabling or dis-
abling the POR18 detector. The Power-on Reset generated by the POR18 detector can be
ignored by writing a one to the POR18 Mask bit (VREGCR.POR18MASK). Because of internal
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