AT32UC3L0256 Atmel Corporation, AT32UC3L0256 Datasheet - Page 193

• Manufacturer Part Number: AT32UC3L0256
• Manufacturer: Atmel Corporation

Specifications of AT32UC3L0256

• Flash (kbytes): 256 Kbytes
• Pin Count: 48
• Max. Operating Frequency: 50 MHz
• Cpu: 32-bit AVR
• # Of Touch Channels: 17
• Hardware Qtouch Acquisition: Yes
• Max I/o Pins: 36
• Ext Interrupts: 36
• Usb Speed: No
• Usb Interface: No
• Spi: 5
• Twi (i2c): 2
• Uart: 4
• Lin: 4
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 8
• Adc Resolution (bits): 12
• Adc Speed (ksps): 460
• Analog Comparators: 8
• Resistive Touch Screen: No
• Temp. Sensor: Yes
• Crypto Engine: No
• Sram (kbytes): 16
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: Yes
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.62 to 3.6
• Operating Voltage (vcc): 1.62 to 3.6
• Fpu: No
• Mpu / Mmu: Yes / No
• Timers: 6
• Output Compare Channels: 18
• Input Capture Channels: 12
• Pwm Channels: 35
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

32145A–12/2011
only be executed if the Dithering Enable bit (DITHER) in DFLLnCONF has been written to a one.
If DITHER is written to a zero DFLLnLOCKA will never occur. If dithering is enabled, the fre-
quency of the dithering is decided by a generic clock (CLK_DFLLIF_DITHER). This clock has to
be set up correctly before enabling dithering. Please refer to the Generic Clocks section for
details.
Figure 13-3. DFLL Closed loop State Diagram
When dithering is enabled the accuracy of the average output frequency of the DFLL will be
higher. However, the actual frequency will be alternating between two frequencies. If a fixed fre-
quency is required, the dithering should not be enabled.
Figure 13-4. DFLL Locking in Closed loop
CLK_DFLL is ready to be used when the DFLLn Synchronization Ready bit (DFLLnRDY) in
PCLKSR is set after enabling the DFLL. However, the accuracy of the output frequency depends
on which locks are set.
For lock times, please refer to the Electrical Characteristics chapter.
DFLLnLOCKC
Calculate
COARSE
Measure
value
f
new
DFLLn
0
frequency
frequency
Target
Initial
1
DFLLnLOCKF
new FINE
Calculate
value
0
DFLLnLOCKC DFLLnLOCKF DFLLnLOCKA
1
Compen-
DITHER
sate for
drift
0
AT32UC3L0128/256
1
DFLLnLOCKA
Calculate
dutycycle
dithering
new
0
1
Compen-
sate for
drift
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