AT32UC3L0256 Atmel Corporation, AT32UC3L0256 Datasheet - Page 524
AT32UC3L0256
Manufacturer Part Number
AT32UC3L0256
Description
Manufacturer
Atmel Corporation
Datasheets
1.AT32UC3A0128.pdf
(377 pages)
2.AT32UC3A0128.pdf
(159 pages)
3.AT32UC3L0128.pdf
(85 pages)
4.AT32UC3L0128.pdf
(852 pages)
Specifications of AT32UC3L0256
Flash (kbytes)
256 Kbytes
Pin Count
48
Max. Operating Frequency
50 MHz
Cpu
32-bit AVR
# Of Touch Channels
17
Hardware Qtouch Acquisition
Yes
Max I/o Pins
36
Ext Interrupts
36
Usb Speed
No
Usb Interface
No
Spi
5
Twi (i2c)
2
Uart
4
Lin
4
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
8
Adc Resolution (bits)
12
Adc Speed (ksps)
460
Analog Comparators
8
Resistive Touch Screen
No
Temp. Sensor
Yes
Crypto Engine
No
Sram (kbytes)
16
Self Program Memory
YES
Dram Memory
No
Nand Interface
No
Picopower
Yes
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.62 to 3.6
Operating Voltage (vcc)
1.62 to 3.6
Fpu
No
Mpu / Mmu
Yes / No
Timers
6
Output Compare Channels
18
Input Capture Channels
12
Pwm Channels
35
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
AT32UC3L0256-D3HR
Manufacturer:
ATMEL/爱特梅尔
Quantity:
20 000
Company:
Part Number:
AT32UC3L0256-H
Manufacturer:
ATMEL
Quantity:
270
Part Number:
AT32UC3L0256-H
Manufacturer:
ATMEL/爱特梅尔
Quantity:
20 000
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22.9.7
Name:
Access Type:
Offset:
Reset Value:
• BTF: Byte Transfer Finished
• REP: Repeated Start Received
• STO: Stop Received
• SMBDAM: SMBus Default Address Match
• SMBHHM: SMBus Host Header Address Match
• SMBALERTM: SMBus Alert Response Address Match
• GCM: General Call Match
• SAM: Slave Address Match
• BUSERR: Bus Error
32145A–12/2011
ORUN
BTF
31
23
15
7
-
-
This bit is cleared when the corresponding bit in SCR is written to one.
This bit is set when byte transfer has completed.
This bit is cleared when the corresponding bit in SCR is written to one.
This bit is set when a REPEATED START condition is received.
This bit is cleared when the corresponding bit in SCR is written to one.
This bit is set when the STOP condition is received.
This bit is cleared when the corresponding bit in SCR is written to one.
This bit is set when the received address matched the SMBus Default Address.
This bit is cleared when the corresponding bit in SCR is written to one.
This bit is set when the received address matched the SMBus Host Header Address.
This bit is cleared when the corresponding bit in SCR is written to one.
This bit is set when the received address matched the SMBus Alert Response Address.
This bit is cleared when the corresponding bit in SCR is written to one.
This bit is set when the received address matched the General Call Address.
This bit is cleared when the corresponding bit in SCR is written to one.
This bit is set when the received address matched the Slave Address.
This bit is cleared when the corresponding bit in SCR is written to one.
This bit is set when a misplaced START or STOP condition has occurred.
Status Register
BUSERR
URUN
REP
30
22
14
6
-
SR
Read-only
0x18
0x000000002
SMBPECERR
STO
TRA
29
21
13
5
-
SMBTOUT
SMBDAM
28
20
12
4
-
-
SMBHHM
TCOMP
27
19
11
3
-
-
SMBALERTM
SEN
26
18
10
2
-
-
AT32UC3L0128/256
TXRDY
GCM
25
17
9
1
-
-
RXRDY
SAM
NAK
24
16
8
0
-
524
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