AT32UC3L0256 Atmel Corporation, AT32UC3L0256 Datasheet - Page 108

• Manufacturer Part Number: AT32UC3L0256
• Manufacturer: Atmel Corporation

Specifications of AT32UC3L0256

• Flash (kbytes): 256 Kbytes
• Pin Count: 48
• Max. Operating Frequency: 50 MHz
• Cpu: 32-bit AVR
• # Of Touch Channels: 17
• Hardware Qtouch Acquisition: Yes
• Max I/o Pins: 36
• Ext Interrupts: 36
• Usb Speed: No
• Usb Interface: No
• Spi: 5
• Twi (i2c): 2
• Uart: 4
• Lin: 4
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 8
• Adc Resolution (bits): 12
• Adc Speed (ksps): 460
• Analog Comparators: 8
• Resistive Touch Screen: No
• Temp. Sensor: Yes
• Crypto Engine: No
• Sram (kbytes): 16
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: Yes
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.62 to 3.6
• Operating Voltage (vcc): 1.62 to 3.6
• Fpu: No
• Mpu / Mmu: Yes / No
• Timers: 6
• Output Compare Channels: 18
• Input Capture Channels: 12
• Pwm Channels: 35
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

9.5.4.1
9.5.5
32145A–12/2011
Interrupts
Operation example
Figure 9-2
als, and a SAU with multiple channels and an Unlock Register (UR). Imagine that the MPU has
been set up to disallow all accesses from the CPU to the grey modules. Thus the CPU has no
way of accessing for example the Transmit Holding register in the UART, present on address X
on the bus. Note that the SAU RTRs are not protected by the MPU, thus the RTRs can be
accessed. If for example RTR0 is configured to point to address X, an access to RTR0 will be
remapped by the SAU to address X according to the algorithm presented above. By program-
ming the SAU RTRs, specific addresses in modules that have generally been protected by the
MPU can be performed.
Figure 9-2.
The SAU can generate an interrupt request to signal different events. All events that can gener-
ate an interrupt request have dedicated bits in the Status Register (SR). An interrupt request will
be generated if the corresponding bit in the Interrupt Mask Register (IMR) is set. Bits in IMR are
set by writing a one to the corresponding bit in the Interrupt Enable Register (IER), and cleared
by writing a one to the corresponding bit in the Interrupt Disable Register (IDR). The interrupt
request remains active until the corresponding bit in SR is cleared by writing a one to the corre-
sponding bit in the Interrupt Clear Register (ICR).
The following SR bits are used for signalling the result of SAU accesses:
• RTR Address Error (RTRADR) is set if an illegal address is written to the RTRs. Only
• Master Interface Bus Error (MBERROR) is set if any of the conditions listed in
addresses in the range 0xFFFC0000-0xFFFFFFFF are allowed.
occurred.
CHANNEL
shows a typical memory map, consisting of some memories, some simple peripher-
CONFIG
UART
SAU
SAU
Example Memory Map for a System with SAU
Transmit Holding
Receive Holding
Channel 1
Baudrate
Control
RTR62
RTR1
RTR0
UR
AT32UC3L0128/256
Address X
Address Z
Section 9.5.7
108