AT32UC3L0256 Atmel Corporation, AT32UC3L0256 Datasheet - Page 533

• Manufacturer Part Number: AT32UC3L0256
• Manufacturer: Atmel Corporation

Specifications of AT32UC3L0256

• Flash (kbytes): 256 Kbytes
• Pin Count: 48
• Max. Operating Frequency: 50 MHz
• Cpu: 32-bit AVR
• # Of Touch Channels: 17
• Hardware Qtouch Acquisition: Yes
• Max I/o Pins: 36
• Ext Interrupts: 36
• Usb Speed: No
• Usb Interface: No
• Spi: 5
• Twi (i2c): 2
• Uart: 4
• Lin: 4
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 8
• Adc Resolution (bits): 12
• Adc Speed (ksps): 460
• Analog Comparators: 8
• Resistive Touch Screen: No
• Temp. Sensor: Yes
• Crypto Engine: No
• Sram (kbytes): 16
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: Yes
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.62 to 3.6
• Operating Voltage (vcc): 1.62 to 3.6
• Fpu: No
• Mpu / Mmu: Yes / No
• Timers: 6
• Output Compare Channels: 18
• Input Capture Channels: 12
• Pwm Channels: 35
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

23. Pulse Width Modulation Controller (PWMA)
23.1
23.2
32145A–12/2011
Features
Overview
Rev: 2.0.1.0
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The Pulse Width Modulation Controller (PWMA) controls several pulse width modulation (PWM)
channels. The number of channels is specific to the device. Each channel controls one square
output PWM waveform. Characteristics of the output PWM waveforms such as period and duty
cycle are configured through the user interface. All user interface registers are mapped on the
peripheral bus.
The duty cycle value for each channel can be set independently, while the period is determined
by a common timebase counter (TC). The timebase for the counter is selected by using the allo-
cated asynchronous Generic Clock (GCLK). The user interface for the PWMA contains
handshake and synchronizing logic to ensure that no glitches occur on the output PWM wave-
forms while changing the duty cycle values.
PWMA duty cycle values can be changed using two approaches, either an interlinked single-
value mode or an interlinked multi-value mode. In the interlinked single-value mode, any set of
channels, up to 32 channels, can be updated simultaneously with the same value while the other
channels remain unchanged. There is also an interlinked multi-value mode, where the 8 least
significant bits of up to 4 channels can be updated with 4 different values while the other chan-
nels remain unchanged.
Some pins can be driven in open drain mode, allowing the PWMA to generate a 5V waveform
using an external pullup resistor.
Left-aligned non-inverted 8-bit PWM
Common 8-bit timebase counter
Separate 8-bit duty cycle register per channel
Synchronized channel updates
Interlinked operation supported
Interrupt on PWM timebase overflow
Incoming peripheral events supported
One output peripheral event supported
Output PWM waveforms
Open drain driving on selected pins for 5V PWM operation
– Asynchronous clock source supported
– Spread-spectrum counter to allow a constantly varying duty cycle
– No glitches when changing the duty cycles
– Up to 32 channels can be updated with the same duty cycle value at a time
– Up to 4 channels can be updated with different duty cycle values at a time
– Pre-defined channels support incoming (increase/decrease) peripheral events from the
– Incoming increase/decrease event can either increase or decrease the duty cycle by one
– Connected to channel 0 and asserted when the common timebase counter is equal to the
– Support normal waveform output for each channel
– Support composite waveform generation (XOR’ed) for each pair channels
Peripheral Event System
programmed duty cycle for channel 0
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