AT32UC3L0256 Atmel Corporation, AT32UC3L0256 Datasheet - Page 192

• Manufacturer Part Number: AT32UC3L0256
• Manufacturer: Atmel Corporation

Specifications of AT32UC3L0256

• Flash (kbytes): 256 Kbytes
• Pin Count: 48
• Max. Operating Frequency: 50 MHz
• Cpu: 32-bit AVR
• # Of Touch Channels: 17
• Hardware Qtouch Acquisition: Yes
• Max I/o Pins: 36
• Ext Interrupts: 36
• Usb Speed: No
• Usb Interface: No
• Spi: 5
• Twi (i2c): 2
• Uart: 4
• Lin: 4
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 8
• Adc Resolution (bits): 12
• Adc Speed (ksps): 460
• Analog Comparators: 8
• Resistive Touch Screen: No
• Temp. Sensor: Yes
• Crypto Engine: No
• Sram (kbytes): 16
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: Yes
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.62 to 3.6
• Operating Voltage (vcc): 1.62 to 3.6
• Fpu: No
• Mpu / Mmu: Yes / No
• Timers: 6
• Output Compare Channels: 18
• Input Capture Channels: 12
• Pwm Channels: 35
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

13.5.4.5
32145A–12/2011
Closed loop operation
FINE, be aware that the output frequency must not exceed the maximum frequency of the
device after the division in the clock generator. It is possible to change the value of COARSE
and FINE, and thereby the output frequency of the DFLL, while the DFLL is enabled and in use.
The DFLL clock is ready to be used when PCLKSR.DFLLnRDY is cleared after enabling the
DFLL.
The frequency range in open loop mode is 20-150MHz, but maximum frequency can be higher,
and the minimum frequency can be lower. The best way to start the DFLL at a specific frequency
in open loop mode is to first configure it for closed loop mode, see
is achieved, read back the COARSE and FINE values and switch to open loop mode using these
values. An alternative approach is to use the Frequency Meter (FREQM) to monitor the DFLL
frequency and adjust the COARSE and FINE values based on measurement results form the
FREQM. Please refer to the FREQM chapter for more information on how to use it. Note that the
output frequency of the DFLL will drift when in open loop mode due to temperature and voltage
changes. Please refer to the Electrical Characteristics chapter for details.
The DFLL must be correctly configured before closed loop operation can be enabled. After
e n a b l i n g t h e D F L L , e n a b l e a n d s e l e c t a r e f e r e n c e c l o c k ( C L K _ D F L L I F _ R E F ) .
CLK_DFLLIF_REF is a generic clock, please refer to Generic Clocks section for details. Then
set the maximum step size allowed in finding the COARSE and FINE values by setting the
Coarse Maximum Step field (CSTEP) and Fine Maximum Step field (FSTEP) in the DFLLn Max-
imum Step Register (DFLLnSTEP). A small step size will ensure low overshoot on the output
frequency, but can typically result in longer lock times. A high value might give a big overshoot,
but can typically give faster locking. DFLLnSTEP.CSTEP and DFLLnSTEP.FSTEP must be
lower than 50% of the maximum value of DFLLnCONF.COARSE and DFLLnCONF.FINE
respectively. Then select the multiplication factor in the Integer Multiply Factor field (IMUL) and
the Fractional Multiply field (FMUL) in the DFLLn Multiplier Register (DFLLnMUL). Care must be
taken when choosing IMUL and FMUL so the output frequency does not exceed the maximum
frequency of the device. Start the closed loop mode by writing a one to DFLLnCONF.MODE bit.
The frequency of CLK_DFLL (f
where f
only in closed loop mode, and are controlled by the DFLLIF to meet user specified frequency.
The values in COARSE when the closed loop mode is enabled is used by the frequency tuner as
a starting point for COARSE. Setting COARSE to a value close to the final value will reduce the
time needed to get a lock on COARSE.
Frequency locking
The locking of the frequency in closed loop mode is divided into three stages. In the COARSE
stage the control logic quickly finds the correct value for DFLLnCONF.COARSE and thereby
sets the output frequency to a value close to the correct frequency. The DFLLn Locked on
Coarse Value bit (DFLLnLOCKC) in PCLKSR will be set when this is done. In the FINE stage the
control logic tunes the value in DFLLnCONF.FINE so the output frequency will be very close to
the desired frequency. DFLLn Locked on Fine Value bit (DFLLnLOCKF) in PCLKSR will be set
when this is done. In the ACCURATE stage the DFLL frequency tuning mechanism uses dither-
ing on the FINE bits to obtain an accurate average output frequency. DFLLn Locked on Accurate
Value bit (DFLLnLOCKA) in PCLKSR will be set when this is done. The ACCURATE stage will
REF
is the frequency of CLK_DFLLIF_REF. COARSE and FINE in DFLLnCONF are read-
DFLL
f
) is given by:
DFLL
=
⎛
⎝
IMUL
+
FMUL
---------------- -
2
16
⎞ f
⎠
REF
AT32UC3L0128/256
Section
13.5.4.5. When a lock
192