AT32UC3L0256 Atmel Corporation, AT32UC3L0256 Datasheet - Page 105

• Manufacturer Part Number: AT32UC3L0256
• Manufacturer: Atmel Corporation

Specifications of AT32UC3L0256

• Flash (kbytes): 256 Kbytes
• Pin Count: 48
• Max. Operating Frequency: 50 MHz
• Cpu: 32-bit AVR
• # Of Touch Channels: 17
• Hardware Qtouch Acquisition: Yes
• Max I/o Pins: 36
• Ext Interrupts: 36
• Usb Speed: No
• Usb Interface: No
• Spi: 5
• Twi (i2c): 2
• Uart: 4
• Lin: 4
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 8
• Adc Resolution (bits): 12
• Adc Speed (ksps): 460
• Analog Comparators: 8
• Resistive Touch Screen: No
• Temp. Sensor: Yes
• Crypto Engine: No
• Sram (kbytes): 16
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: Yes
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.62 to 3.6
• Operating Voltage (vcc): 1.62 to 3.6
• Fpu: No
• Mpu / Mmu: Yes / No
• Timers: 6
• Output Compare Channels: 18
• Input Capture Channels: 12
• Pwm Channels: 35
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

9.3
32145A–12/2011
Block Diagram
Figure 9-1
some peripherals, and a bus system. The SAU is connected to both the Peripheral Bus (PB) and
the High Speed Bus (HSB). Configuration of the SAU is done via the PB, while memory
accesses are done via the HSB. The SAU receives an access on its HSB slave interface,
remaps it, checks that the channel is unlocked, and if so, initiates a transfer on its HSB master
interface to the remapped address.
The thin arrows in
read the RX Buffer in the USART. The MPU has been configured to protect all registers in the
USART from user mode access, while the SAU has been configured to remap the RX Buffer into
a memory space that is not protected by the MPU. This unprotected memory space is mapped
into the SAU HSB slave space. When the CPU reads the appropriate address in the SAU, the
SAU will perform an access to the desired RX buffer register in the USART, and thereafter return
the read results to the CPU. The return data flow will follow the opposite direction of the control
flow arrows in
Figure 9-1.
Interrupt
request
Bus slave
presents the SAU integrated in an example system with a CPU, some memories,
Figure
Bus master
SAU Block Diagram
SAU Configuration
MPU
CPU
SAU Channel
Figure 9-1
9-1.
SAU
exemplifies control flow when using the SAU. The CPU wants to
Bus master
Bus slave
Flash
Bus slave
USART
AT32UC3L0128/256
PWM
High Speed Bus
Bus slave
RAM
Bus bridge
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