AT32UC3L0256 Atmel Corporation, AT32UC3L0256 Datasheet - Page 545

• Manufacturer Part Number: AT32UC3L0256
• Manufacturer: Atmel Corporation

Specifications of AT32UC3L0256

• Flash (kbytes): 256 Kbytes
• Pin Count: 48
• Max. Operating Frequency: 50 MHz
• Cpu: 32-bit AVR
• # Of Touch Channels: 17
• Hardware Qtouch Acquisition: Yes
• Max I/o Pins: 36
• Ext Interrupts: 36
• Usb Speed: No
• Usb Interface: No
• Spi: 5
• Twi (i2c): 2
• Uart: 4
• Lin: 4
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 8
• Adc Resolution (bits): 12
• Adc Speed (ksps): 460
• Analog Comparators: 8
• Resistive Touch Screen: No
• Temp. Sensor: Yes
• Crypto Engine: No
• Sram (kbytes): 16
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: Yes
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.62 to 3.6
• Operating Voltage (vcc): 1.62 to 3.6
• Fpu: No
• Mpu / Mmu: Yes / No
• Timers: 6
• Output Compare Channels: 18
• Input Capture Channels: 12
• Pwm Channels: 35
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

23.7.4
Name:
Access Type:
Offset:
Reset Value:
•
Note:
32145A–12/2011
SELn: Channel Select
31
23
15
7
The duty cycle of the PWMA channel SELn will be updated with the value stored in the IMDUTY.DUTYn field when IMCHSEL is
written. If SELn points to a non-implemented channel, the write will be discarded.
The duty registers will be updated with the value stored in the IMDUTY.DUTY3, IMDUTY.DUTY2, IMDUTY.DUTY1 and
IMDUTY.DUTY0 fields when the IMCHSEL register is written. Synchronization takes place immediately when an IMCHSEL reg-
ister is written. The duty cycle registers will, however, not be updated until the synchronization is completed and the timebase
counter reaches its top value in order to avoid glitches.
Interlinked Multiple Value Channel Select
30
22
14
6
IMCHSEL
Write-only
0x0C
0x00000000
29
21
13
5
28
20
12
4
SEL3
SEL2
SEL1
SEL0
27
19
11
3
26
18
10
2
AT32UC3L0128/256
25
17
9
1
24
16
8
0
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