AT32UC3L0256 Atmel Corporation, AT32UC3L0256 Datasheet - Page 23

• Manufacturer Part Number: AT32UC3L0256
• Manufacturer: Atmel Corporation

Specifications of AT32UC3L0256

• Flash (kbytes): 256 Kbytes
• Pin Count: 48
• Max. Operating Frequency: 50 MHz
• Cpu: 32-bit AVR
• # Of Touch Channels: 17
• Hardware Qtouch Acquisition: Yes
• Max I/o Pins: 36
• Ext Interrupts: 36
• Usb Speed: No
• Usb Interface: No
• Spi: 5
• Twi (i2c): 2
• Uart: 4
• Lin: 4
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 8
• Adc Resolution (bits): 12
• Adc Speed (ksps): 460
• Analog Comparators: 8
• Resistive Touch Screen: No
• Temp. Sensor: Yes
• Crypto Engine: No
• Sram (kbytes): 16
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: Yes
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.62 to 3.6
• Operating Voltage (vcc): 1.62 to 3.6
• Fpu: No
• Mpu / Mmu: Yes / No
• Timers: 6
• Output Compare Channels: 18
• Input Capture Channels: 12
• Pwm Channels: 35
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

4.4
4.4.1
4.4.2
32145A–12/2011
Programming Model
Register File Configuration
Status Register Configuration
The AVR32UC register file is shown below.
Figure 4-3.
The Status Register (SR) is split into two halfwords, one upper and one lower, see
and
and L bits, while the upper halfword contains information about the mode and state the proces-
sor executes in. Refer to the AVR32 Architecture Manual for details.
Figure 4-4.
Application
Bit 31
Bit 31
SP_APP
SS
INT0PC
INT1PC
FINTPC
0
SMPC
R12
R11
R10
PC
LR
SR
R9
R8
R7
R6
R5
R4
R3
R2
R1
R0
Figure
LC
Bit 0
1
0
-
Supervisor
Bit 31
0
4-5. The lower word contains the C, Z, N, V, and Q condition code flags and the R, T,
-
SP_SYS
INT0PC
INT1PC
FINTPC
SMPC
R12
R11
R10
PC
LR
R9
R8
R7
R6
R5
R4
R3
R2
R1
R0
SR
The AVR32UC Register File
The Status Register High Halfword
0
-
Bit 0
DM
0
INT0
Bit 31
SP_SYS
INT0PC
INT1PC
FINTPC
SMPC
D
0
R12
R11
R10
PC
LR
R9
R8
R7
R6
R5
R4
R3
R2
R1
R0
SR
Bit 0
0
-
INT1
Bit 31
M 2
0
SP_SYS
FINTPC
INT0PC
INT1PC
SMPC
R12
R11
R10
PC
LR
R9
R8
R7
R6
R5
R4
R3
R2
R1
R0
SR
M 1
0
Bit 0
M 0
1
INT2
Bit 31
SP_SYS
FINTPC
INT0PC
INT1PC
SMPC
EM
R12
R11
R10
1
PC
LR
R9
R8
R7
R6
R5
R4
R3
R2
R1
R0
SR
SS_STATUS
Bit 0
SS_SP_SYS
SS_SP_APP
SS_ADRR
SS_ADRF
SS_ADR0
SS_ADR1
I3M
SS_RAR
SS_RSR
0
INT3
Bit 31
I2M
FE
0
SP_SYS
INT0PC
INT1PC
FINTPC
SMPC
R12
R11
R10
PC
LR
R9
R8
R7
R6
R5
R4
R3
R2
R1
R0
SR
I1M
AT32UC3L0128/256
0
Bit 0
I0M
0
Exception
Bit 31
SP_SYS
INT0PC
INT1PC
FINTPC
SMPC
Bit 16
R12
R11
R10
G M
PC
LR
R9
R8
R7
R6
R5
R4
R3
R2
R1
R0
SR
1
Bit 0
Bit nam e
Initial value
G lobal Interrupt M ask
Interrupt Level 0 M ask
Interrupt Level 1 M ask
Interrupt Level 2 M ask
Interrupt Level 3 M ask
Exception M ask
M ode Bit 0
M ode Bit 1
M ode Bit 2
Reserved
Debug State
Debug State M ask
Reserved
Secure State
NMI
Bit 31
SP_SYS
INT0PC
INT1PC
FINTPC
SMPC
R12
R11
R10
PC
LR
R9
R8
R7
R6
R5
R4
R3
R2
R1
R0
SR
Bit 0
Figure 4-4
Secure
Bit 31
SP_SEC
INT0PC
INT1PC
FINTPC
SMPC
R12
R11
R10
PC
SR
LR
R9
R8
R7
R6
R5
R4
R3
R2
R1
R0
Bit 0
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