AT32UC3L0256 Atmel Corporation, AT32UC3L0256 Datasheet - Page 154

• Manufacturer Part Number: AT32UC3L0256
• Manufacturer: Atmel Corporation

Specifications of AT32UC3L0256

• Flash (kbytes): 256 Kbytes
• Pin Count: 48
• Max. Operating Frequency: 50 MHz
• Cpu: 32-bit AVR
• # Of Touch Channels: 17
• Hardware Qtouch Acquisition: Yes
• Max I/o Pins: 36
• Ext Interrupts: 36
• Usb Speed: No
• Usb Interface: No
• Spi: 5
• Twi (i2c): 2
• Uart: 4
• Lin: 4
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 8
• Adc Resolution (bits): 12
• Adc Speed (ksps): 460
• Analog Comparators: 8
• Resistive Touch Screen: No
• Temp. Sensor: Yes
• Crypto Engine: No
• Sram (kbytes): 16
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: Yes
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.62 to 3.6
• Operating Voltage (vcc): 1.62 to 3.6
• Fpu: No
• Mpu / Mmu: Yes / No
• Timers: 6
• Output Compare Channels: 18
• Input Capture Channels: 12
• Pwm Channels: 35
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

12.6.1.3
12.6.2
12.6.2.1
12.6.3
32145A–12/2011
Peripheral Clock Masking
Sleep Modes
Clock Ready flag
Cautionary note
Similarly, the PBx clocks can be divided by writing their respective Clock Select (PBxSEL) regis-
ters to get the divided PBx frequency:
f
The PBx clock frequency can not exceed the CPU clock frequency. The user must select a PBx-
SEL.PBSEL value greater than or equal to the CPUSEL.CPUSEL value, so that f
user selects division factors that will result in f
change the PBxSEL.PBSEL/PBDIV values to ensure correct operation (f
The HSB clock will always be forced to the same division as the CPU clock.
To ensure correct operation, the frequencies must never exceed the specified maximum fre-
quency for each clock domain.
For modules connected to the HSB bus, the PB clock frequency must be the same as the CPU
clock frequency.
There is a slight delay from CPUSEL and PBxSEL being written to the new clock setting taking
effect. During this interval, the Clock Ready bit in the Status Register (SR.CKRDY) will read as
zero. When the clock settings change is completed, the bit will read as one. The Clock Select
registers (CPUSEL, PBxSEL) must not be written to while SR.CKRDY is zero, or the system
may become unstable or hang.
The Clock Ready bit in the Interrupt Status Register (ISR.CKRDY) is set on a SR.CKRDY zero-
to-one transition. If the Clock Ready bit in the Interrupt Mask Register (IMR.CKRDY) is set, an
interrupt request is generated. IMR.CKRDY is set by writing a one to the corresponding bit in the
Interrupt Enable Register (IER.CKRDY).
By default, the clocks for all modules are enabled, regardless of which modules are actually
being used. It is possible to disable the clock for a module in the CPU, HSB, or PBx clock
domain by writing a zero to the corresponding bit in the corresponding Clock Mask (CPU-
MASK/HSBMASK/PBxMASK) register. When a module is not clocked, it will cease operation,
and its registers cannot be read nor written. The module can be re-enabled later by writing a one
to the corresponding mask bit. A module may be connected to several clock domains, in which
case it will have several mask bits. The Maskable Module Clocks table in the Clock Mask regis-
ter description contains a list of implemented maskable clocks.
Note that clocks should only be switched off if it is certain that the module will not be used.
Switching off the clock for the Flash Controller will cause a problem if the CPU needs to read
from the flash. Switching off the clock to the Power Manager, which contains the mask registers,
or the corresponding PBx bridge, will make it impossible to write to the mask registers again. In
this case, they can only be re-enabled by a system reset.
In normal operation, all clock domains are active, allowing software execution and peripheral
operation. When the CPU is idle, it is possible to switch it and other (optional) clock domains off
to save power. This is done by the sleep instruction, which takes the sleep mode index number
from
PBx
= f
Table 12-2 on page 155
main
/ 2
(PBSEL+1)
as argument.
CPU
< f
PBx
, the Power Manager will automatically
AT32UC3L0128/256
CPU
f
PBx
CPU
).
f
PBx
. If the
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