AT32UC3L0256 Atmel Corporation, AT32UC3L0256 Datasheet - Page 376

• Manufacturer Part Number: AT32UC3L0256
• Manufacturer: Atmel Corporation

Specifications of AT32UC3L0256

• Flash (kbytes): 256 Kbytes
• Pin Count: 48
• Max. Operating Frequency: 50 MHz
• Cpu: 32-bit AVR
• # Of Touch Channels: 17
• Hardware Qtouch Acquisition: Yes
• Max I/o Pins: 36
• Ext Interrupts: 36
• Usb Speed: No
• Usb Interface: No
• Spi: 5
• Twi (i2c): 2
• Uart: 4
• Lin: 4
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 8
• Adc Resolution (bits): 12
• Adc Speed (ksps): 460
• Analog Comparators: 8
• Resistive Touch Screen: No
• Temp. Sensor: Yes
• Crypto Engine: No
• Sram (kbytes): 16
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: Yes
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.62 to 3.6
• Operating Voltage (vcc): 1.62 to 3.6
• Fpu: No
• Mpu / Mmu: Yes / No
• Timers: 6
• Output Compare Channels: 18
• Input Capture Channels: 12
• Pwm Channels: 35
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

19. Universal Synchronous Asynchronous Receiver Transmitter (USART)
19.1
19.2
32145A–12/2011
Features
Overview
Rev: 4.4.0.6
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The Universal Synchronous Asynchronous Receiver Transceiver (USART) provides a full
duplex, universal, synchronous/asynchronous serial link. Data frame format is widely configu-
rable, including basic length, parity, and stop bit settings, maximizing standards support. The
receiver implements parity-, framing-, and overrun error detection, and can handle un-fixed
frame lengths with the time-out feature. The USART supports several operating modes, provid-
ing an interface to, LIN, and SPI buses and infrared transceivers. Communication with slow and
remote devices is eased by the timeguard. Duplex multidrop communication is supported by
address and data differentiation through the parity bit. The hardware handshaking feature
enables an out-of-band flow control, automatically managing RTS and CTS pins. The Peripheral
DMA Controller connection enables memory transactions, and the USART supports chained
Configurable baud rate generator
5- to 9-bit full-duplex, synchronous and asynchronous, serial communication
SPI Mode
LIN Mode
Test Modes
Supports two Peripheral DMA Controller channels
– 1, 1.5, or 2 stop bits in asynchronous mode, and 1 or 2 in synchronous mode
– Parity generation and error detection
– Framing- and overrun error detection
– MSB- or LSB-first
– Optional break generation and detection
– Receiver frequency over-sampling by 8 or 16 times
– Optional RTS-CTS hardware handshaking
– Receiver Time-out and transmitter Timeguard
– Optional Multidrop mode with address generation and detection
– Master or slave
– Configurable serial clock phase and polarity
– CLK SPI serial clock frequency up to a quarter of the CLK_USART internal clock frequency
– Compliant with LIN 1.3 and LIN 2.0 specifications
– Master or slave
– Processing of Frames with up to 256 data bytes
– Configurable response data length, optionally defined automatically by the Identifier
– Self synchronization in slave node configuration
– Automatic processing and verification of the “Break Field” and “Sync Field”
– The “Break Field” is detected even if it is partially superimposed with a data byte
– Optional, automatic identifier parity management
– Optional, automatic checksum management
– Supports both “Classic” and “Enhanced” checksum types
– Full LIN error checking and reporting
– Frame Slot Mode: the master allocates slots to scheduled frames automatically.
– Wakeup signal generation
– Automatic echo, remote- and local loopback
– Buffer transfers without processor intervention
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