AT32UC3L0256 Atmel Corporation, AT32UC3L0256 Datasheet - Page 447
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AT32UC3L0256
Manufacturer Part Number
AT32UC3L0256
Description
Manufacturer
Atmel Corporation
Datasheets
1.AT32UC3A0128.pdf
(377 pages)
2.AT32UC3A0128.pdf
(159 pages)
3.AT32UC3L0128.pdf
(85 pages)
4.AT32UC3L0128.pdf
(852 pages)
Specifications of AT32UC3L0256
Flash (kbytes)
256 Kbytes
Pin Count
48
Max. Operating Frequency
50 MHz
Cpu
32-bit AVR
# Of Touch Channels
17
Hardware Qtouch Acquisition
Yes
Max I/o Pins
36
Ext Interrupts
36
Usb Speed
No
Usb Interface
No
Spi
5
Twi (i2c)
2
Uart
4
Lin
4
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
8
Adc Resolution (bits)
12
Adc Speed (ksps)
460
Analog Comparators
8
Resistive Touch Screen
No
Temp. Sensor
Yes
Crypto Engine
No
Sram (kbytes)
16
Self Program Memory
YES
Dram Memory
No
Nand Interface
No
Picopower
Yes
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.62 to 3.6
Operating Voltage (vcc)
1.62 to 3.6
Fpu
No
Mpu / Mmu
Yes / No
Timers
6
Output Compare Channels
18
Input Capture Channels
12
Pwm Channels
35
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
AT32UC3L0256-D3HR
Manufacturer:
ATMEL/爱特梅尔
Quantity:
20 000
Company:
Part Number:
AT32UC3L0256-H
Manufacturer:
ATMEL
Quantity:
270
Part Number:
AT32UC3L0256-H
Manufacturer:
ATMEL/爱特梅尔
Quantity:
20 000
- AT32UC3A0128 PDF datasheet
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- AT32UC3L0128 PDF datasheet #3
- AT32UC3L0128 PDF datasheet #4
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- Download datasheet (13Mb)
20.8.5
Name:
Access Type:
Offset:
Reset Value:
• SPIENS: SPI Enable Status
• UNDES: Underrun Error Status (Slave Mode Only)
• TXEMPTY: Transmission Registers Empty
• NSSR: NSS Rising
• OVRES: Overrun Error Status
• MODF: Mode Fault Error
• TDRE: Transmit Data Register Empty
• RDRF: Receive Data Register Full
32145A–12/2011
31
23
15
7
-
-
-
-
1: This bit is set when the SPI is enabled.
0: This bit is cleared when the SPI is disabled.
1: This bit is set when a transfer begins whereas no data has been loaded in the TDR register.
0: This bit is cleared when the SR register is read.
1: This bit is set when TDR and internal shifter are empty. If a transfer delay has been defined, TXEMPTY is set after the
completion of such delay.
0: This bit is cleared as soon as data is written in TDR.
1: A rising edge occurred on NSS pin since last read.
0: This bit is cleared when the SR register is read.
1: This bit is set when an overrun has occurred. An overrun occurs when RDR is loaded at least twice from the serializer since
the last read of the RDR.
0: This bit is cleared when the SR register is read.
1: This bit is set when a Mode Fault occurred.
0: This bit is cleared when the SR register is read.
1: This bit is set when the last data written in the TDR register has been transferred to the serializer.
0: This bit is cleared when data has been written to TDR and not yet transferred to the serializer.
TDRE equals zero when the SPI is disabled or at reset. The SPI enable command sets this bit to one.
1: Data has been received and the received data has been transferred from the serializer to RDR since the last read of RDR.
0: No data has been received since the last read of RDR
Status Register
30
22
14
6
-
-
-
-
SR
Read-only
0x10
0x00000000
29
21
13
5
-
-
-
-
28
20
12
4
-
-
-
-
OVRES
27
19
11
3
-
-
-
UNDES
MODF
26
18
10
2
-
-
AT32UC3L0128/256
TXEMPTY
TDRE
25
17
9
1
-
-
SPIENS
NSSR
RDRF
24
16
8
0
-
447
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