AT32UC3L0256 Atmel Corporation, AT32UC3L0256 Datasheet - Page 538

• Manufacturer Part Number: AT32UC3L0256
• Manufacturer: Atmel Corporation

Specifications of AT32UC3L0256

• Flash (kbytes): 256 Kbytes
• Pin Count: 48
• Max. Operating Frequency: 50 MHz
• Cpu: 32-bit AVR
• # Of Touch Channels: 17
• Hardware Qtouch Acquisition: Yes
• Max I/o Pins: 36
• Ext Interrupts: 36
• Usb Speed: No
• Usb Interface: No
• Spi: 5
• Twi (i2c): 2
• Uart: 4
• Lin: 4
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 8
• Adc Resolution (bits): 12
• Adc Speed (ksps): 460
• Analog Comparators: 8
• Resistive Touch Screen: No
• Temp. Sensor: Yes
• Crypto Engine: No
• Sram (kbytes): 16
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: Yes
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.62 to 3.6
• Operating Voltage (vcc): 1.62 to 3.6
• Fpu: No
• Mpu / Mmu: Yes / No
• Timers: 6
• Output Compare Channels: 18
• Input Capture Channels: 12
• Pwm Channels: 35
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

23.6.6.2
32145A–12/2011
Interlinked Multiple Value PWM Operation
(ISDUTY) register. Each channel has a corresponding enabling bit in the Interlinked Single
Value Channel Set (ISCHSET) register(s). When a bit is written to one in the ISCHSET register,
the duty cycle register for the corresponding channel will be updated with the value stored in the
ISDUTY register. It can only be updated when the READY bit in the Status Register
(SR.READY) is one, indicating that the PWMA is ready for writing.
shows the writing procedure. It is thus possible to update the duty cycle values for up to 32 PWM
channels within one ISCHSET register at a time.
Figure 23-3. Interlinked Single Value PWM Operation Flow
The interlinked multiple value PWM operation allows up to four channels to be updated simulta-
neously with different duty cycle values. The four duty cycle values are required to be written to
the four fields IMDUTY.DUTY3, IMDUTY.DUTY2, IMDUTY.DUTY1 and IMDUTY.DUTY0,
respectively. The index number of the four channels to be updated is written to the four SEL
fields in the Interlinked Multiple Value Channel Select (IMCHSEL) register (IMCHSEL.SEL).
When the IMCHSEL register is written, the values stored in IMDUTY register are synchronized
to the duty cycle registers for the channels selected by the SEL fields.
shows the writing procedure.
Note that only writes to the implemented channels will be effective. If one of the IMCHSEL.SEL
fields points to a non-existing channel, the corresponding value in the IMDUTY.DUTYx field will
not be written. If the same channel is specified multiple times in the IMCHSEL.SEL fields, the
channel will be updated with the value referred by the upper IMCHSEL.SEL field.
Figure 23-4. Interlinked Multiple Value PWM Operation Flow
Channeln
DUTY
Channeln
DUTY
...
DUTY3/2/1/0
ISDUTY
IMDUTY
Channel2
DUTY
...
Channel1
DUTY
Channel1
ISCHSETm
IMCHSEL
MUX
DUTY
Channel0
AT32UC3L0128/256
DUTY
Channel0
DUTY
Enable
Write
Figure 23-3 on page 538
Figure 23-4 on page 538
538