AT32UC3L0256 Atmel Corporation, AT32UC3L0256 Datasheet - Page 157

• Manufacturer Part Number: AT32UC3L0256
• Manufacturer: Atmel Corporation

Specifications of AT32UC3L0256

• Flash (kbytes): 256 Kbytes
• Pin Count: 48
• Max. Operating Frequency: 50 MHz
• Cpu: 32-bit AVR
• # Of Touch Channels: 17
• Hardware Qtouch Acquisition: Yes
• Max I/o Pins: 36
• Ext Interrupts: 36
• Usb Speed: No
• Usb Interface: No
• Spi: 5
• Twi (i2c): 2
• Uart: 4
• Lin: 4
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 8
• Adc Resolution (bits): 12
• Adc Speed (ksps): 460
• Analog Comparators: 8
• Resistive Touch Screen: No
• Temp. Sensor: Yes
• Crypto Engine: No
• Sram (kbytes): 16
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: Yes
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.62 to 3.6
• Operating Voltage (vcc): 1.62 to 3.6
• Fpu: No
• Mpu / Mmu: Yes / No
• Timers: 6
• Output Compare Channels: 18
• Input Capture Channels: 12
• Pwm Channels: 35
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

12.6.4
12.6.4.1
12.6.4.2
32145A–12/2011
Shutdown Sleep Mode
Entering Shutdown sleep mode
Description
Communication between the synchronous clock domains is disturbed when entering and exiting
sleep modes. Bus transactions over clock domains affected by the sleep mode are therefore not
recommended. The system may hang if the bus clocks are stopped during a bus transaction.
The CPU is automatically stopped in a safe state to ensure that all CPU bus operations are com-
plete when the sleep mode goes into effect. Thus, when entering Idle mode, no further action is
necessary.
When entering a sleep mode (except Idle mode), all HSB masters must be stopped before
entering the sleep mode. In order to let potential PBx write operations complete, the user should
let the CPU perform a PBx register read operation before issuing the sleep instruction. This will
stall the CPU until pending PBx operations have completed.
The Shutdown sleep mode requires extra care. Please refer to
The Shutdown sleep mode is available only when the device is used in the “3.3V supply mode,
with 1.8V regulated I/O lines“ configuration (refer to the Power Considerations chapter). In this
configuration, the voltage regulator supplies both VDDCORE and VDDIO power supplies.
When the device enters Shutdown mode, the regulator is turned off and only the following logic
is kept powered by VDDIN:
The table below lists I/O line functionality that remains operational during Shutdown sleep mode.
If no special function is used the I/O line will keep its setting when entering the sleep mode
Table 12-4.
Before entering the Shutdown sleep mode, a few actions are required:
Pin
PA11
PA13
PA20
PA21
PB04
PB05
PB10
RESET_N
– OSC32K using alternate pinout PA13/PA20
– AST core logic (internal counter and alarm detection logic)
– Backup Registers
– I/O lines PA11, PA13, PA20, PA21, PB04, PB05, and PB10
– RESET_N line
– All modules should normally be disabled before entering Shutdown sleep mode (see
Section
I/O Lines Usage During Shutdown Mode
12.6.3.5)
Possible Usage During Shutdown Sleep Mode
WAKE_N signal (active low wake-up)
XIN32_2 (OSC32K using alternate pinout)
XOUT32_2 (OSC32K using alternate pinout)
Reset pin
AT32UC3L0128/256
Section
12.6.4.
157