AT32UC3L0256 Atmel Corporation, AT32UC3L0256 Datasheet - Page 204

• Manufacturer Part Number: AT32UC3L0256
• Manufacturer: Atmel Corporation

Specifications of AT32UC3L0256

• Flash (kbytes): 256 Kbytes
• Pin Count: 48
• Max. Operating Frequency: 50 MHz
• Cpu: 32-bit AVR
• # Of Touch Channels: 17
• Hardware Qtouch Acquisition: Yes
• Max I/o Pins: 36
• Ext Interrupts: 36
• Usb Speed: No
• Usb Interface: No
• Spi: 5
• Twi (i2c): 2
• Uart: 4
• Lin: 4
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 8
• Adc Resolution (bits): 12
• Adc Speed (ksps): 460
• Analog Comparators: 8
• Resistive Touch Screen: No
• Temp. Sensor: Yes
• Crypto Engine: No
• Sram (kbytes): 16
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: Yes
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.62 to 3.6
• Operating Voltage (vcc): 1.62 to 3.6
• Fpu: No
• Mpu / Mmu: Yes / No
• Timers: 6
• Output Compare Channels: 18
• Input Capture Channels: 12
• Pwm Channels: 35
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

Figure 13-9. Fractional Prescaler Jitter Examples
13.5.15
32145A–12/2011
FPCLK
SRC clock
FMUL= 5
FDIV=5
FMUL=3
FDIV=10
FMUL=7
FDIV=9
Generic Clocks
The user must configure the FP frequency by writing to the FPMUL and FPDIV fields of the
FPMUL and FPDIV registers. FPMUL and FPDIV must not be equal to zero and FPDIV must be
greater or equal to FPMUL. This results in the output frequency:
The CKSEL field can not be changed dynamically but the FPMUL and FPDIV fields can be
changed on-the-fly.
As described in
clock period but are not always equals. However the difference between the low level half period
length and the high level half period length is at the most one source clock period.
This induces when FPDIV is not an integer multiple of FPMUL a jitter on the FPCLK. The more
the FPCLK frequency is low, the more the jitter incidence is reduced.
Rev: 1.1.0.0
Timers, communication modules, and other modules connected to external circuitry may require
specific clock frequencies to operate correctly. The SCIF defines a number of generic clocks that
can provide a wide range of accurate clock frequencies.
Each generic clock runs from either clock source listed in the “Generic Clock Sources” table in
the SCIF Module Configuration section. The selected source can optionally be divided by any
even integer up to 512. Each clock can be independently enabled and disabled, and is also
automatically disabled along with peripheral clocks by the Sleep Controller in the Power
Manager.
• Jitter description
f
FPCLK
= f
SRC
Figure
* FPMUL/ (2*FPDIV)
13-9, the CLKFP half period lengths are integer multiples of the source
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