AT32UC3L0256 Atmel Corporation, AT32UC3L0256 Datasheet - Page 517

• Manufacturer Part Number: AT32UC3L0256
• Manufacturer: Atmel Corporation

Specifications of AT32UC3L0256

• Flash (kbytes): 256 Kbytes
• Pin Count: 48
• Max. Operating Frequency: 50 MHz
• Cpu: 32-bit AVR
• # Of Touch Channels: 17
• Hardware Qtouch Acquisition: Yes
• Max I/o Pins: 36
• Ext Interrupts: 36
• Usb Speed: No
• Usb Interface: No
• Spi: 5
• Twi (i2c): 2
• Uart: 4
• Lin: 4
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 8
• Adc Resolution (bits): 12
• Adc Speed (ksps): 460
• Analog Comparators: 8
• Resistive Touch Screen: No
• Temp. Sensor: Yes
• Crypto Engine: No
• Sram (kbytes): 16
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: Yes
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.62 to 3.6
• Operating Voltage (vcc): 1.62 to 3.6
• Fpu: No
• Mpu / Mmu: Yes / No
• Timers: 6
• Output Compare Channels: 18
• Input Capture Channels: 12
• Pwm Channels: 35
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

22.9.1
Name:
Access Type:
Offset:
Reset Value:
• TENBIT: Ten Bit Address Match
• ADR: Slave Address
• SODR: Stretch Clock on Data Byte Reception
• SOAM: Stretch Clock on Address Match
• CUP: NBYTES Count Up
• ACK: Slave Receiver Data Phase ACK Value
• PECEN: Packet Error Checking Enable
• SMHH: SMBus Host Header
• SMDA: SMBus Default Address
• SMBALERT: SMBus Alert
32145A–12/2011
SWRST
SODR
31
23
15
7
-
0: Disables Ten Bit Address Match.
1: Enables Ten Bit Address Match.
Slave address used in slave address match. Bits 9:0 are used if in 10-bit mode, bits 6:0 otherwise.
0: Does not stretch bus clock immediately before ACKing a received data byte.
1: Stretches bus clock immediately before ACKing a received data byte.
0: Does not stretch bus clock after address match.
1: Stretches bus clock after address match.
0: Causes NBYTES to count down (decrement) per byte transferred.
1: Causes NBYTES to count up (increment) per byte transferred.
0: Causes a low value to be returned in the ACK cycle of the data phase in slave receiver mode.
1: Causes a high value to be returned in the ACK cycle of the data phase in slave receiver mode.
0: Disables SMBus PEC (CRC) generation and check.
1: Enables SMBus PEC (CRC) generation and check.
0: Causes the TWIS not to acknowledge the SMBus Host Header.
1: Causes the TWIS to acknowledge the SMBus Host Header.
0: Causes the TWIS not to acknowledge the SMBus Default Address.
1: Causes the TWIS to acknowledge the SMBus Default Address.
0: Causes the TWIS to release the SMBALERT line and not to acknowledge the SMBus Alert Response Address (ARA).
1: Causes the TWIS to pull down the SMBALERT line and to acknowledge the SMBus Alert Response Address (ARA).
Control Register
SOAM
30
22
14
6
-
-
CR
Read/Write
0x00
0x00000000
CUP
29
21
13
5
-
-
STREN
ACK
28
20
12
4
-
ADR[7:0]
GCMATCH
PECEN
27
19
11
3
-
SMATCH
TENBIT
SMHH
26
18
10
2
AT32UC3L0128/256
SMEN
SMDA
25
17
9
1
ADR[9:8]
SMBALERT
SEN
24
16
8
0
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