AT32UC3L0256 Atmel Corporation, AT32UC3L0256 Datasheet - Page 115

• Manufacturer Part Number: AT32UC3L0256
• Manufacturer: Atmel Corporation

Specifications of AT32UC3L0256

• Flash (kbytes): 256 Kbytes
• Pin Count: 48
• Max. Operating Frequency: 50 MHz
• Cpu: 32-bit AVR
• # Of Touch Channels: 17
• Hardware Qtouch Acquisition: Yes
• Max I/o Pins: 36
• Ext Interrupts: 36
• Usb Speed: No
• Usb Interface: No
• Spi: 5
• Twi (i2c): 2
• Uart: 4
• Lin: 4
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 8
• Adc Resolution (bits): 12
• Adc Speed (ksps): 460
• Analog Comparators: 8
• Resistive Touch Screen: No
• Temp. Sensor: Yes
• Crypto Engine: No
• Sram (kbytes): 16
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: Yes
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.62 to 3.6
• Operating Voltage (vcc): 1.62 to 3.6
• Fpu: No
• Mpu / Mmu: Yes / No
• Timers: 6
• Output Compare Channels: 18
• Input Capture Channels: 12
• Pwm Channels: 35
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

9.6.5
Name:
Access Type:
Offset:
Reset Value:
• IDLE
• SEN: SAU Setup Mode Enable
• EN: SAU Enabled
• RTRADR: RTR Address Error
• MBERROR: Master Interface Bus Error
• URES: Unlock Register Error Status
• URKEY: Unlock Register Key Error
• URREAD: Unlock Register Read
32145A–12/2011
RTRADR
31
23
15
7
-
-
-
This bit is cleared when a read or write operation to the SAU channel is started.
This bit is set when the operation is completed and no SAU bus operations are pending.
This bit is cleared when the SAU exits setup mode.
This bit is set when the SAU enters setup mode.
This bit is cleared when the SAU is disabled.
This bit is set when the SAU is enabled.
This bit is cleared when the corresponding bit in ICR is written to one.
This bit is set if, in the configuration phase, an RTR was written with an illegal address, i.e. the upper 16 bits in the address were
different from 0xFFFC, 0xFFFD, 0xFFFE or 0xFFFF.
This bit is cleared when the corresponding bit in ICR is written to one.
This bit is set if a channel access generated a transfer on the master interface that received a bus error response from the
addressed slave.
This bit is cleared when the corresponding bit in ICR is written to one.
This bit is set if an attempt was made to unlock a channel by writing to the Unlock Register while one or more error bits were set
in SR. The unlock operation was aborted.
This bit is cleared when the corresponding bit in ICR is written to one.
This bit is set if the Unlock Register was attempted written with an invalid key.
This bit is cleared when the corresponding bit in ICR is written to one.
This bit is set if the Unlock Register was read.
Status Register
MBERROR
30
22
14
6
-
-
-
SR
Read-only
0x10
0x00000400
URES
29
21
13
5
-
-
-
URKEY
28
20
12
4
-
-
-
URREAD
27
19
11
3
-
-
-
IDLE
CAU
26
18
10
2
-
-
AT32UC3L0128/256
SEN
CAS
25
17
9
1
-
-
EXP
EN
24
16
8
0
-
-
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