AT32UC3L0256 Atmel Corporation, AT32UC3L0256 Datasheet - Page 107

• Manufacturer Part Number: AT32UC3L0256
• Manufacturer: Atmel Corporation

Specifications of AT32UC3L0256

• Flash (kbytes): 256 Kbytes
• Pin Count: 48
• Max. Operating Frequency: 50 MHz
• Cpu: 32-bit AVR
• # Of Touch Channels: 17
• Hardware Qtouch Acquisition: Yes
• Max I/o Pins: 36
• Ext Interrupts: 36
• Usb Speed: No
• Usb Interface: No
• Spi: 5
• Twi (i2c): 2
• Uart: 4
• Lin: 4
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 8
• Adc Resolution (bits): 12
• Adc Speed (ksps): 460
• Analog Comparators: 8
• Resistive Touch Screen: No
• Temp. Sensor: Yes
• Crypto Engine: No
• Sram (kbytes): 16
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: Yes
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.62 to 3.6
• Operating Voltage (vcc): 1.62 to 3.6
• Fpu: No
• Mpu / Mmu: Yes / No
• Timers: 6
• Output Compare Channels: 18
• Input Capture Channels: 12
• Pwm Channels: 35
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

9.5.2.1
9.5.3
9.5.4
32145A–12/2011
Lock Mechanism
Normal Operation
Protecting SAU configuration registers
In order to prevent the SAU configuration registers to be changed by malicious or runaway code,
they should be protected by the MPU as soon as they have been configured. Maximum security
is provided in the system if program memory does not contain any code to unprotect the config-
uration registers in the MPU. This guarantees that runaway code can not accidentally unprotect
and thereafter change the SAU configuration registers.
The SAU can be configured to use two different access mechanisms: Open and Locked. In
Open Mode, SAU channels can be accessed freely after they have been configured and
enabled. In order to prevent accidental accesses to remapped addresses, it is possible to config-
ure the SAU in Locked Mode. Writing a one to the Open Mode bit in the CONFIG register
(CONFIG.OPEN) will enable Open Mode. Writing a zero to CONFIG.OPEN will enable Locked
Mode.
When using Locked Mode, the lock mechanism must be configured by writing a user defined key
value to the Unlock Key (UKEY) field in the Configuration Register (CONFIG). The number of
CLK_SAU_HSB cycles the channel remains unlocked must be written to the Unlock Number of
Clock Cycles (UCYC) field in CONFIG.
Access control to the SAU channels is enabled by means of the Unlock Register (UR), which
resides in the same address space as the SAU channels. Before a channel can be accessed,
the unlock register must be written with th correct key and channel number (single write access).
Access to the channel is then permitted for the next CONFIG.UCYC clock cycles, or until a suc-
cessful access to the unlocked channel has been made.
Only one channel can be unlocked at a time. If any other channel is unlocked at the time of writ-
ing UR, this channel will be automatically locked before the channel addressed by the UR write
is unlocked.
An attempted access to a locked channel will be aborted, and the Channel Access Unsuccessful
bit (SR.CAU) will be set.
Any pending errors bits in SR must be cleared before it is possible to access UR. The following
SR bits are defined as error bits: EXP, CAU, URREAD, URKEY, URES, MBERROR, RTRADR.
If any of these bits are set while writing to UR, the write is aborted and the Unlock Register Error
Status (URES) bit in SR is set.
The following sequence must be used in order to access a SAU channel in normal operation
(CR.SEN=0):
1. If not in Open Mode, write the unlock key to UR.KEY and the channel number to
2. Perform the read or write operation to the SAU channel. If not in Open Mode, this must
3. To confirm that the access was successful, wait for the IDLE transfer status bit
UR.CHANNEL.
be done within CONFIG.UCYC clock cycles of unlocking the channel. The SAU will use
its HSB master interface to remap the access to the target address pointed to by the
corresponding RTR.
(SR.IDLE) to indicate the operation is completed. Then check SR for possible error con-
ditions. The SAU can be configured to generate interrupt requests or a Bus Error
Exception if the access failed.
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