AT32UC3L0256 Atmel Corporation, AT32UC3L0256 Datasheet - Page 153

• Manufacturer Part Number: AT32UC3L0256
• Manufacturer: Atmel Corporation

Specifications of AT32UC3L0256

• Flash (kbytes): 256 Kbytes
• Pin Count: 48
• Max. Operating Frequency: 50 MHz
• Cpu: 32-bit AVR
• # Of Touch Channels: 17
• Hardware Qtouch Acquisition: Yes
• Max I/o Pins: 36
• Ext Interrupts: 36
• Usb Speed: No
• Usb Interface: No
• Spi: 5
• Twi (i2c): 2
• Uart: 4
• Lin: 4
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 8
• Adc Resolution (bits): 12
• Adc Speed (ksps): 460
• Analog Comparators: 8
• Resistive Touch Screen: No
• Temp. Sensor: Yes
• Crypto Engine: No
• Sram (kbytes): 16
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: Yes
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.62 to 3.6
• Operating Voltage (vcc): 1.62 to 3.6
• Fpu: No
• Mpu / Mmu: Yes / No
• Timers: 6
• Output Compare Channels: 18
• Input Capture Channels: 12
• Pwm Channels: 35
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

12.6
12.6.1
Figure 12-2. Synchronous Clock Generation
12.6.1.1
12.6.1.2
32145A–12/2011
Main Clock
Sources
Functional Description
Synchronous Clocks
Selecting the main clock source
Selecting synchronous clock division ratio
MCSEL
The System RC Oscillator (RCSYS) and a selection of other clock sources can provide the
source for the main clock, which is the origin for the synchronous CPU/HSB and PBx module
clocks. For details about the other main clock sources, please refer to the Main Clock Control
(MCCTRL) register description. The synchronous clocks can run of the main clock and all the 8-
bit prescaler settings as long as f
the fly, according to variations in application load. The clock domains can be shut down in sleep
mode, as described in
can be individually masked to minimize power consumption in inactive modules.
The common main clock can be connected to RCSYS or a selection of other clock sources. For
details about the other main clock sources, please refer to the MCCTRL register description. By
default, the main clock will be connected to RCSYS. The user can connect the main clock to
another source by writing to the Main Clock Select (MCCTRL.MCSEL) field. The user must first
assure that the source is enabled and ready in order to avoid a deadlock. Care should also be
taken so that the new synchronous clock frequencies do not exceed the maximum frequency for
each clock domain.
The main clock feeds an 8-bit prescaler, which can be used to generate the synchronous clocks.
By default, the synchronous clocks run on the undivided main clock. The user can select a pres-
caler division for the CPU clock by writing a one to the CPU Division bit in the CPU Clock Select
register (CPUSEL.CPUDIV), and a value to the CPU Clock Select field (CPUSEL.CPUSEL),
resulting in a CPU clock frequency:
Prescaler
f
CPU
= f
Instruction
main
Sleep
/ 2
(CPUSEL+1)
CPUSEL
Section
CPUDIV
0
1
12.6.3. The module clocks in every synchronous clock domain
CPU
Controller
Main Clock
Sleep
f
PBx,
. The synchronous clock source can be changed on-
CPUMASK
AT32UC3L0128/256
Mask
CPU Clocks
HSB Clocks
PBx Clocks
153