MMCCMB2107 Freescale, MMCCMB2107 Datasheet - Page 96

• Manufacturer Part Number: MMCCMB2107
• Manufacturer: Freescale

Specifications of MMCCMB2107

• Lead Free Status / RoHS Status: Not Compliant

Chip Configuration Module (CCM)
Technical Data
96
NOTE:
SZEN — TSIZ[1:0] Enable Bits
PSTEN — PSTAT[3:0] Signal Enable Bits
SHINT — Show Interrupt Bit
The FRCRSTOUT function in the reset controller has a higher priority
than the SHINT function.
BME — Bus Monitor External Enable Bit
BMD — Bus Monitor Debug Mode Bit
This read/write bit enables the TSIZ[1:0] function of the external pins.
This read/write bit enables the PSTAT[3:0] function of the external
pins.
The SHINT bit allows visibility to any active interrupt request to the
processor. If the SHINT bit is set, the RSTOUT pin is the OR of the
fast and normal interrupt signals.
The SHINT bit is read/write always.
The BME bit enables the bus monitor to operate during external bus
cycles.
Table 3-2
The BMD bit controls how the bus monitor responds during debug
mode.
This bit is read/write always.
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1 = TSIZ[1:0] function enabled
0 = TSIZ[1:0] function disabled
1 = PSTAT[3:0] function enabled
0 = PSTAT[3:0] function disabled
1 = Internal requests reflected on RSTOUT pin
0 = Normal RSTOUT pin function
1 = Bus monitor enabled on external bus cycles
0 = Bus monitor disabled on external bus cycles
1 = Bus monitor enabled in debug mode
0 = Bus monitor disabled in debug mode
Chip Configuration Module (CCM)
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shows the read/write accessibility of this write-once bit.
MMC2107 – Rev. 2.0
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