MMCCMB2107 Freescale, MMCCMB2107 Datasheet - Page 231

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MMCCMB2107

Manufacturer Part Number
MMCCMB2107
Description
Manufacturer
Freescale
Datasheet

Specifications of MMCCMB2107

Lead Free Status / RoHS Status
Not Compliant
MMC2107 – Rev. 2.0
MOTOROLA
PLLMODE — Clock Mode Bit
PLLSEL — PLL Select Bit
PLLREF — PLL Reference Bit
LOCKS — Sticky PLL Lock Bit
The MODE bit is configured at reset and reflects the clock mode as
shown in
The PLLSEL bit is configured at reset and reflects the PLL mode as
shown in
The PLLREF bit is configured at reset and reflects the PLL reference
source in normal PLL mode as shown in
The LOCKS flag is a sticky indication of PLL lock status.
The lock detect function sets the LOCKS bit when the PLL achieves
lock after:
When the PLL loses lock, LOCKS is cleared. When the PLL relocks,
LOCKS remains cleared until one of the two listed events occurs.
Freescale Semiconductor, Inc.
MODE:PLLSEL:PLLREF
For More Information On This Product,
1 = PLL clock mode
0 = External clock mode
1 = Normal PLL mode
0 = 1:1 PLL mode
1 = Crystal clock reference
0 = External clock reference
1 = No unintentional PLL loss of lock since last system reset or
0 = PLL loss of lock since last system reset or MFD change or
– A system reset, or
– A write to SYNCR that changes the MFD[2:0] bits
MFD change
currently not locked due to exit from STOP with FWKUP set
Table
Table
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000
100
110
111
Table 10-5. System Clock Modes
Clock Module
10-5.
10-5.
External clock mode
1:1 PLL mode
Normal PLL mode with external clock reference
Normal PLL mode with crystal oscillator
reference
Clock Mode
Table
Memory Map and Registers
10-5.
Technical Data
Clock Module
231